Presentation + Paper
20 March 2020 On product overlay metrology challenges in advanced nodes
Author Affiliations +
Abstract
On product overlay (OPO) challenges are quickly becoming yield limiters for the latest technology nodes, requiring new and innovative metrology solutions. In this paper we will cover current and future overlay trends in logic and memory device processing. We will review new lithography overlay challenges and node-after-node trends in the OPO error budget for advanced logic, DRAM, and 3D NAND devices. The central question of this paper is whether optical overlay metrology can keep up with challenges that include accuracy, intra-field variability, target-to-device offset, and others. After surveying the two dominant technologies in optical overlay metrology (IBO and SCOL®), we will outline innovative solutions that will help to address metrology challenges for the new device nodes.
Conference Presentation
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrei Shchegrov, Philippe Leray, Yuri Paskover, Liran Yerushalmi, Efi Megged, Yoav Grauer, and Roel Gronheid "On product overlay metrology challenges in advanced nodes", Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113251P (20 March 2020); https://doi.org/10.1117/12.2551932
Lens.org Logo
CITATIONS
Cited by 2 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Optical parametric oscillators

Metrology

Overlay metrology

Logic

Optical alignment

Semiconducting wafers

3D metrology

Back to Top