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20 March 2020 Improving after-etch overlay performance using high-density in-device metrology in DRAM manufacturing
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In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM)[1] allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ik-Hyun Jeong, Seung-Woo Koo, Hyun-Sok Kim, Jung-Il Hwang, Dong-Jin Lee, Min-Shik Kim, Jae-Wuk Ju, Kang-Min Lee, Young-Sik Kim, Cees Lambregts, Rizvi Rahman, Marc Hauptmann, Raheleh Pishkari, Allwyn Boustheen, Kwang-Young Hu, Paul Böcker, Dong-Hak Lee, In-Ho Joo, and Kang-San Lee "Improving after-etch overlay performance using high-density in-device metrology in DRAM manufacturing", Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113252X (20 March 2020);

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