This PDF file contains the front matter associated with SPIE Proceedings Volume 11327, including the title page, copyright information, table of contents, and author and conference committee lists.

In the field of microlithography, conventional computers are widely used for mask optimization. Recent progress of quantum and quantum-inspired computers has encouraged the development of quantum algorithms for numerous applications. So far, no method has been established for solving mask optimization problems with quantum computers. We introduced a simple model that describes the mask optimization problem as a quadratic unconstrained binary optimization (QUBO) problem, which is easily implemented on these computers. For simplicity, we assume there exists a target image profile on the wafer. The target can be the image of an existing mask or a virtual ideal mask which may be designed as a pixelated mask having a continuous transmission distribution. The solution is evaluated as the difference between the simulated image profile on the wafer surface and the target profile.

Since its introduction at Luminescent Technologies and continued development at Synopsys, Inverse Lithography Technology (ILT) has delivered industry leading quality of results (QOR) for mask synthesis designs. With the advent of powerful, widely deployed, and user-friendly machine learning (ML) training techniques, we are now able to exploit the quality of ILT masks in a ML framework which has significant runtime benefits. In this paper we will describe our MLILT flow including training data selection and preparation, network architectures, training techniques, and analysis tools. Typically, ILT usage has been limited to smaller areas owing to concerns like runtime, solution consistency, and mask shape complexity. We will exhibit how machine learning can be used to overcome these challenges, thereby providing a pathway to extend ILT solution to full chip logic design. We will demonstrate the clear superiority of ML-ILT QOR over existing mask synthesis techniques, such as rule based placements, that have similar runtime performance.

Inspired by many success stories of machine learning (ML) in a broad range of artificial intelligence (AI) applications, both industrial and academic researchers are now actively developing ML solutions for challenging problems in computational lithography. In this work, we explore the possibility of utilizing ML software and hardware platforms for mask synthesis applications. Specifically, we demonstrate a standalone mask synthesis flow that runs entirely on the TensorFlow ML platform with a reinforcement learning (RL) approach and GPU acceleration. We will describe the architecture of our ML mask synthesis framework that comprises separable and interchangeable components including neural network (NN)-based 3D mask, imaging and resist models. We will discuss the readiness of these components and present the proof-of-concept evaluation results of the proposed ML mask synthesis framework.

Achieving stitchless full chip ILT in a day through a combination of mathematics and physics, high performance computing (HPC) methods, GPU acceleration, and tailoring our computational design platform (CDP) to the task is discussed.

Key factors for maximizing yield in a modern semiconductor fab for Memory device manufacturing include wafer critical dimension uniformity and accuracy control. Resolution Enhancement Techniques (RET) solutions for the highly repetitive arrayed memory devices have been driven by the need for perfect geometric consistency without compromising the lithographic quality. Traditionally, both optical proximity correction (OPC) and sub-resolution assist features (SRAFs) insertion for these repetitive cell-array structures have been dealt by applying manual hand-crafted or rule-based methods. But these can be prone to iterative human intervention, long runtimes and sub-par lithographic quality. This work adopts a pattern/property aware approach (PA)2 and cell-array OPC technology that leverage the inherent repetitive and hierarchical structure of the cell-array to ensure the lithographic quality and perfect geometric consistency and symmetry down to the level of feature edges with model-based OPC and rule-based SRAF solutions. The flow also demonstrates a drastic reduction in runtime and turn-around-time to mask tapeouts for the full chip (core and periphery).

Computational lithography has been playing a critical role in enabling the semiconductor industry. After source mask co-optimization (SMO), inverse lithography has become the ultimate frontier of computational lithography. Full chip implementation of rigorous inverse lithography remains impractical because of enormous computational hardware resource requirements and long computational time, the situation exacerbates for EUV computational lithography where mask 3D effect is more pronounced. One very promising technique to overcome the barrier is to take full advantage of the maturing machine learning techniques based on neural network architecture. Some success has been achieved using deep convolution neural network (DCNN) to obtain inverse lithography technology (ILT) solution with significantly less computational time. In DCNN, to extract features with sufficient resolution and nearly complete representation, the feature extract layers are very complicated and lack of physical meaning. More importantly, the training requires large number of well balanced samples, which makes the training more difficult and time consuming. To alleviate the difficulties relating to DCNN, we have proposed the physics based optimal feature vector design for machine learning based computational lithography. The innovative physics based feature vector design eliminates the need of feature extraction layers in neural network, only layers for mapping function construction are needed, which greatly reduces the NN training time and accelerates the NN model SRAF generation for full chip. In this paper, we will present our machine learning based inverse lithography results with adaptive and dynamical sampling scheme for neural network training.

The semiconductor design node shrinking requires tighter edge placement errors (EPE) budget. OPC error, as one major contributor of EPE budget, need to be reduced with better OPC model accuracy. In addition, the CD (Critical Dimension) shrinkage in advanced node heavily relies on the etch process. Therefore AEI (After Etch Inspection) metrology and modeling are important to provide accurate pattern correction and optimization. For nodes under 14nm, the etch bias (i.e. the bias between ADI (After Development Inspection) CD and AEI CD) could be -10 nm ~ -50 nm, with a strong loading and aspect-ratio dependency. Etch behavior in advanced node is very complicated and brings challenges to conventional rule based OPC correction. Therefore, accurate etch modeling becomes more and more important to make precise prediction of final complex shapes on wafer for OPC correction. In order to ensure the accuracy of etch modeling, high quality metrology is necessary to reduce random error and systematic measurement error. Moreover, CD gauges alone are not sufficient to capture all the effects of the etch process on different patterns. Edge placement (EP) gauges that accurately describe the contour shapes at various key positions are needed. In this work we used the AEI SEM images obtained from traditional CD-SEM flow, processed with ASML’s MXP (Metrology for eXtreme Performance) tool, and used the extracted CD gauges and massive EP gauges to train a deeplearning Newron Etch model. In the approach, MXP reduced the AEI metrology random errors and shape fitting measurement error and provides better pattern coverage with massive reliable CD and EP gauges, Newron Etch captures complex and unknown physical and chemical effects learned from wafer data. Results shows that MXP successfully extracted stable contour from AEI SEM for various pattern types. Three etch models are calibrated and compared: CD based EEB model (Effective Etch Bias), CD+EP based EEB model, and CD+EP based Newron etch model. CD based EEB model captures the major trend of the etch process. Including EP gauges helps EEB model with about 10% RMS reduction on prediction. Integration of MXP (CD+EP) and Newron Etch model gains about 45% prediction RMS reduction compared to baseline model. The good prediction of Newron Etch is also verified from wafer SEM overlay on complex-shape patterns. This result validates the effectiveness of ASML’s solution of deep learning etch model integration with MXP AEI’s massive wafer data extraction from etch process, and will help to provide accurate and reliable etch modeling for advanced node etch OPC correction in semiconductor manufacturing.

Sub-resolution assist features (SRAFs) are inserted in mask layout to improve the manufacturing process window of main patterns. SRAFs should be large enough to maximize their effect, but they are not intended to be printed on photoresist (PR). An accurate method of SRAF printing prediction is important to assure that no SRAFs are actually printed. We apply a machine learning model, specifically artificial neural network (ANN), for fast and accurate SRAF printing check (named ML- SPC). Polar Fourier transform signals and local layout densities are extracted from each SRAF pixel and its surroundings, and are provided to ANN. The area sum of member pixels that are predicted to be printed is used to determine the final printability of SRAF. Training data is carefully sampled so that similar number of printed and non-printed data are used for training; cost function is adjusted in such a way that missing predictions are treated more importantly than false alarms. When ML-SPC is applied to 10nm memory devices, it achieves 11% of false alarms while popular MTA method reports 24%. In addition, ML-SPC is faster than MTA by about 2.7 times.

Background: Critical design configurations, so-called hotspots, have limited lithography process margins and are particularly sensitive to mask topography effects. Unfortunately, hotspot inspection at wafer-level is a costly, timeconsuming and non-exhaustive solution. On the other hand, accurate simulation of hotspots implies a very precise representation of the mask 3-D parameters which are challenging to measure directly on a reticle. Aim: In this work, we propose two complementary methods to characterize accurately hotspots without the need for wafer data. Approach: The first approach is based on Zeiss WLCD-2G aerial image metrology tool able to measure 2-dimensional high-resolution aerial images maps of any mask pattern across different focuses. The second approach uses rigorous simulations relying on very accurate mask parameters calibrated beforehand from the complete information contained in these high-resolution aerial images delivered by WLCD Results: The calibration of the mask parameters improves the matching between simulated and WLCD aerial images by almost 20% with an error of 2% (RMS). We showed with a few examples that hotspots discovered during the wafer patterning can be detected and characterized directly at the mask-level from the measured aerial images or from accurate resist simulations. Conclusions: The good matching between the rigorous simulation and WLCD as well as their capacity to predict hotspots cross-validates both methods. The calibration of the mask parameters also indicated that to achieve an even better matching our description of the mask proximity effect has to be more elaborated.

Corner rounding improvement is critical to device performance, yield, and cell area reduction. In this paper, we present a method to use dual tone sub-resolution assist feature (SRAF) to improve both the outer corner rounding and inner corner rounding which in turn enhance the pattern quality. The simulation data and wafer data are presented. A few parameters have been investigated, such as the position of the SRAF, the shape of the SRAF, resist type and mask tone. The preliminary results show that more than 40% reduction of both inner corner rounding and outer corner rounding can be achieved by placing sub-resolution assist features at appropriate locations. The limit of corner rounding improvement is determined by mask rule check (MRC) and resist sensitivities.

Typical ILT goes through a continuous tone mask to define a greyscale mask for the best process window, followed by a conversion into actual mask geometries, which are typically Manahttanized to be compatible with printing on existing mask writers. On mask, however, the features to be printed are not Manhattan, and we demonstrate that, by not taking into account the actual mask shapes, current Manhattan mask 3D (M3D) approximations using width, shape, and corner libraries, give rise to poor predictions for the final aerial image. Now that curvilinear ILT is possible to manufacture, we introduce a fully curvilinear mask 3D approximations, compatible with ILT masks, that predict the aerial image significantly better than before.

We have previously reported the exact convolution-based analytical solution to the problem of an elastic resist shrinkage during post-exposure baking (PEB). In contrast to the PEB problem, the elastic shrinking during development in general does not admit a strict analytical solution. Here we use a numerical finite element method (FEM) to compare a two-step development/shrinking model to the results of simultaneously solving full set of the development equations with the elastic deformations being accounted for. We also report existence of a strict analytical solution for the shrinking of line and space resist patterns; this constitutes a special 2D shrinking case. The results of analytical and numerical solutions are compared, and are shown to agree. In the final section we formulate novel Elastic Compact Model (ECM) that mechanistically captures shrink-induced biases for the resist walls of arbitrary 2D resist patterns. The model is fast and can be used for the full-chip optical proximity corrections (OPC). The accuracy of ECM is analyzed using typical OPC layouts by comparing to FEM results, rigorous simulations, and SEM measurements.

Lithography simulation is an essential technique for today's semiconductor manufacturing process. Although several rigorous models have been proposed, these methods are time-consuming. In order to calculate a full chip in realistic time, a fast and accurate resist model is essential. This paper proposes a new compact resist model using an arbitrary convolution kernel. The convolution formula can be described as a system of linear equations, therefore, we can determine the convolution kernel by solving the system of linear equations. However, it is hard to find the effective solution, because it is an ill-posed linear inverse problem due to the measurement constraints. Therefore, the key point of our method is how to solve the ill-posed linear inverse problem. In this paper, we explain the details and effectiveness of our method.

The consideration of wafer topography effects in lithographic modeling of implant layers is mandatory for sub 32nm processes. The approximate assumption that both oxide- and resist thickness are independent of pattern design can lead to large model prediction errors and OPC correction failure. An implant lithography modeling flow based on rigorous models is presented that covers a) the STI stack formation and its etch–proximity effects, b) the resist spin-on and resulting thickness fluctuations, c) the image formation in the modeled stack and d) the chemical characterization of implant photoresist. This approach shows accuracy benefits and will be used to augment the existing OPC correction flow.

Measuring properties of ultrathin optical films is based on optical interference. Ultrathin films are very challenging to test, because their thicknesses are far smaller than the measuring wavelength, so very little phase shift can be detected. In this work, test sensitivity and accuracy are improved by a rigorous algorithm in which all unknowns {n,k,t} in their full space are fit together without approximations and presumptions. As a result, a software for variable-angle spectroscopic ellipsometer (VASE) data fitting was developed. It gives very reliable ultrathin-film measurement down to 2.5 nanometers. The software not only improves the reliability, accuracy of {n,k,t} measurement, but it also extends VASE capabilities to characterize a film’s optical quality.

Since its introduction more than a decade ago, inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography. Numerous studies have demonstrated that curvilinear ILT mask shapes produce the best process window. However, the runtimes associated with this computational technique have limited its practical application. In 2019, D2S introduced an entirely new, stitchless approach for ILT [20]. This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. The masks used to validate wafer results for this system were written by a multi-beam mask writer. The question remained of whether it was possible to use this new approach to ILT in a way that could be written by a variable-shaped beam (VSB) mask writer. This paper introduces a new method, in which a process called mask-wafer cooptimization (MWCO) is performed during ILT optimization. This new approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within reasonable write times. It shortens the total turnaround time so that VSB mask writers can produce full-chip, curvilinear ILT masks within a practical, 12-hour time frame, while also producing the largest process windows. It should be noted that this enables curvilinear or any-angle targets for the wafer design to be processed by curvilinear ILT and then written by VSB mask writers for 193i processes. While MWCO as a concept can be used for multi-beam mask writers as well, this paper is focused on MWCO for VSB mask writers.

Markets continuously demand higher resolution and higher productivity in flat panel display (FPD) exposure systems. Our solution to improve resolution and productivity is the use of broadband wavelength illumination. A larger depth of focus (DOF) is also very important to achieve higher productivity because inadequate DOF can cause product defects. To obtain higher resolution and larger DOF, off axis illumination (OAI) conditions have been widely used. OAIs using a narrowband wavelength illumination are well documented and sufficiently studied. On the other hand, Canon FPD exposure tools use a broadband illumination source to achieve higher resolution and productivity. To obtain sufficient OAI effects in broadband exposure lithography, new technology should be developed with consideration of broadband wavelength because OAI effects are different between broadband and narrowband illumination. In this paper we introduce divided spectrum illumination (DSI), a new design concept proposed to achieve both high resolution and large DOF by optimizing the broadband illumination source wavelength band depending on the illumination angle. Experimental imaging results of line and space patterns with a line width of 1.0-μm and pitch of 2.0-μm showed that the DSI design improved resolution. Results showed that test patterns imaged using traditional narrowband OAI could not be resolved at the top of the resist even at the best focus, however resist profiles using DSI were sharp enough to retain pattern fidelity at the top of resist. DOF with DSI also improved 21 % compared to traditional OAI.

Up to now, Miniaturization has been the main drive for improving the performance of semiconductors. And higher performance of semiconductor has been the drive for applications. But miniaturization has become increasingly difficult due to increased power consumption and variations in characteristics. In order to solve these problems, by not only miniaturization of semiconductor elements, but also heterogeneous integration of the IC chips with advanced packaging technology, the higher performance and functionality improvement of the entire system has been proposed and developed. For example, the integrated SoC of the GPU and the High Bandwidth Memory (HBM) via Silicon-interposer(2.5D) are manufactured for high-performance computing, like machine learning and deep learning. With this flow, the wiring of the organic substrate package is also becoming finer line. Furthermore, it is necessary to increase the size of the die. In the following packaging trend, requiring of the Lithography equipment and process for advanced packaging is not only fine wiring to integrate but also large area exposure. In this presentation, we will show the exposure results of various dry film resist by the panel-size lithography system and inspect the state of resolution. The shot size of the lithography system is 250*250mm. Finally, we will discuss the next lithography system and process from the perspective of lithography optics and process.

To handle upcoming advanced technology nodes, the spec of focus control continues to tighten to satisfy more stringent CD uniformity (CDU). In high volume manufacturing (HVM) nowadays, yield at wafer edge suffers from CDU degradation due to process variation like edge roll-off topography. Advance focus control using diffraction-based focus (DBF) was proposed as one solution; we can apply the focus compensation values, which are determined from DBF measurement. However, the confidence of the focus compensation depends on the accuracy of focus measurement, which is a widely recognized challenge in the industry. In this paper, we have investigated the performance and the accuracy of two different designs of DBF marks by collecting full maps of DBF measurements. The measurement shows different signatures cross wafer from the two designs. For focus accuracy validation, CDU maps of several focus sensitive patterns have been collected and analyzed against the defocus measurement results. Our results demonstrate that with the accuracy improved DBF design and focus correction per exposure (CPE) schematic, the CDU is improved by 20%, at the wafer edge. We find that the dimension of the DBF main pattern (W1) dominates the accuracy of focus measurement. A DBF design guideline is proposed that the main pattern dimension (W1) should be close to device focus sensitive pattern size to capture its defocus signature more effectively. The accuracy of focus measurement benefits from designs that are close to device weak point patterns, which in turn improves the overall CD uniformity.

Over the years, lithography engineers have continued to focus on CD control, overlay and process capability to meet node requirements for yield and device performance. The use of ArFi lithography for advanced process nodes demands challenging patterning budget improvements in the sub-nm range.1 In 3D NAND devices, the height differences between the cell and periphery create issues with the ability to adequately image and maintain a useable process window in both regions. Previous work by Fukuda2 developed a multi-exposure technique at multi-focus positions to image contact holes with adequate DOF. Lalovic3 demonstrated a fixed 2 wavelength technique to improve DOF called RELAX. ASML introduced EFESE Rx, a method of tilting the stage during exposure to create multiple focus positions and finally Lalovic4 introduced a broadband laser solution to provide additional DOF. All of these techniques suffered from a number of problems that limited usability. In this work the authors will introduce a new method to increase DOF through alternating wavelength’s from an ArFi light source. This technique, called MFI (multi-focal imaging), can be tuned specifically to provide the required amount of wavelength separation for a specific DOF need. Two focal positions are created that are averaged over the exposure field. The authors will review this wavelength “dithering” approach which can be turned on and off, thus eliminating any potential scanner calibration issues. Initial simulation studies with a fixed source and mask indicated increased DOF with wavelength separation. These DOF improvements have been confirmed with on-wafer single-exposure data. The Tachyon MFI aware engine flow will be reviewed using several customer use cases that have been analyzed to demonstrate maximum DOF and ILS vs wavelength separation. The authors will also review the optimization of new pupils and OPC solutions that are unique with each wavelength separation case and maximize process capability. The presentation will close with a product availability timeline and roadmap.

In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The on-product overlay budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer-to-wafer variation. Due to the complexity, a holistic methodology is used to combine various alignment solutions to achieve the optimal on-product overlay performance. In this paper, we evaluated the holistic method by simulation and experiment for DUV layers. We illustrate the expected on-product overlay improvement.

Even with the large-scale adaption of EUV Lithography to High Volume Manufacturing, numerous device-critical product layers will still be exposed with Immersion Lithography Technology and therefore ZEISS and ASML keep investing in the next generation immersion extensions. The overlay accuracy has to be controlled over the exposure field more accurately and also on a higher spatial frequency grid. To support this functionality, a novel manipulator will be incorporated into the next generation of immersion optics, which is especially well-suited for high frequent distortion tuning. Furthermore, lens distortion measurements and adjustments will be done based on more field points. In this paper, we will show the unique correction functionality of this manipulator and show its various application fields for improving the performance of ASML scanners.

In leading-edge lithography, field-by-field corrections, also known as corrections per exposure, are well established. Many manufacturers use a combination of the traditional higher order wafer and intrafield polynomial corrections, combined with linear field-by-field corrections. However, non-linear wafer deformations are usually strongest at the wafer edge. Therefore, specific high order field-by-field corrections are the ultimate correction method to mitigate the effects of these non-linear wafer deformations. However, determining the appropriate amount of high order field-to-field corrections is not trivial. At the wafer edge, exposure fields are often incomplete, so the fields contain less overlay marks and have a less regular distribution than fields that are completely on the wafer. Therefore, even on dense measurements, it is challenging to model these fields with a high order model without applying overcorrection. On the other hand, the metrology capacity for dense measurements is high, so these can typically only be performed with low frequency. Alternatively, smart field-by-field modeling algorithms are available to compute higher order effects based on reduced sampling plans. In this paper, we study different algorithmic approaches to optimize modeling algorithms for both dense and sparse (reduced) sampling plans. We compare the impact of varying the frequency of dense sampling to the performance of different modeling algorithms on sparse sampling.

In most leading-edge technologies, first layers usually are more critical than later layers. For some technologies, however, most critical layers are in mid-of line. On such technologies, less advanced equipment is used for first layers. Because such tools are not so stable, the overlay variation must be compensated on advanced tools used for later layers. Wafer-to-wafer variation is typically corrected by wafer alignment. By standard wafer alignment, intra-field variations are usually not corrected. Because of the instability of the older tools, additional marks to compensate intra-field variation were measured on advanced tools. This reduces the wafer-to-wafer variation but causes throughput loss. Therefore, sampling plans were optimized to reduce the number of intra-field marks by 50%. This was verified by run-to-run simulations and experiments.

Demand for on-product overlay (OPO) improvement is becoming increasingly crucial in semiconductor manufacturing. Alignment sampling plan is closely linked to OPO. However, alignment sampling plan is constrained by productivity. Inline Alignment Station (iAS) is the groundbreaking system which enable dense alignment without throughput impact. Remaining linear and high order grid of OPO can be corrected with iAS correction. iAS is a measurement tool placed inline with NSR and has its own measurement stage. Therefore, it is possible to measure dense sampling without throughput impact. However, matching two stages generally pose some difficulties. Chucking deformation of wafer is one of the challenging factors. We have overcome the problem by integrating new methods. In this paper, we introduce the detail of the method and show some actual results.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

As the most aggressive features in advanced memory designs continue to shrink, so does the overlay budget. The number of layer stacks also creates unwanted topography, and the alignment robustness of lithography tools becomes much more important for on-product overly. Canon developed a through-the-mask moiré alignment system for the FPA-1200NZ2C nanoimprint lithography (NIL) system allowing high-speed measurement of several alignment marks within each imprint field and alignment compensation to be completed during the imprinting sequence. To provide increased process flexibility and overlay accuracy while maintaining high-productivity, we have developed a new low-noise and high-resolution moiré diffraction alignment system based on spatial phase interferometry. In this paper, we report on the TTM detection system used in FPA-1200NZ2C. In particular, the principle of moiré detection and the improvement of the detection method will be described. The measurement error of moiré is analyzed by a simplified model calculation and we confirmed the relationship between process change and alignment error. Results of analyses proved that selection of the wavelength are key factors for optimizing alignment accuracy. Based on these results we applied the following improvement items: 1) Dual Dipole illumination, 2) Optimization of the alignment wavelength. We evaluated the new alignment system measurement error by comparing the moiré measurement value with the measured overlay values for 24 wafers and confirmed that new TTM alignment system can reduce to the measurement error more than 40%. The data shows that our moiré measurement system can provide process robustness and can support mass-production of leading-edge memory products.

UVLED array aligner for proximity and soft contact exposure has been designed and fabricated. The source is designed for a lithography aligner, each UVLED is arranged in a plate with equal space to form UVLED array source. With AAAAS illumination optics, the aligner is built and has provided the uniformly source. 12 inches wafer with 0.6 micron mask for TSV process has proved in soft contact and proximity exposure modes, with less 1 microns for soft contact. 20 microns for 100 microns proximity exposure, with deviation of 1 micron.

As technology continues to scale aggressively, source mask optimization (SMO) is now a key resolution enhancement technique (RET) to maximize the process window. Synopsys© has developed new source mask optimization tool Proteus SMO that demonstrated this improvement. Proteus SMO is equipped with comprehensive functionalities for computing the optimum source and mask. High flexibilities of source types, mask recipes, models, optimizers, and cost functions are provided. For enabling accurate simulation results, integration of Sentaurus Lithography (S-Litho) is also possible when needed. Moreover, the industrial-proven Inverse Lithography Technology (Proteus ILT) mask synthesis is integrated within Proteus SMO further maximizing the process window. Taking advantage of ILT and SLitho simulation solutions, Proteus SMO could achieve significant lithographic performance improvement.

In modern semiconductor lithography world, doubtlessly, scanners using DUV as light source still be main work horses to push physical limits of semiconductor devices to a new level. Meanwhile, as the semiconductor devices diversified to many different types, for example, logic, DRAM, NAND ash, CMOS Image Sensor (CIS), etc., lithography performances needed are also diversified. For example, CH/VIA layers in the-state-of-the-art logic processes require improved lithography Process Window (PW) due to their shallow Depth of Focus (DOF). On the other hand, engineers working in the field of modern 3D-NAND ash memory and CIS lithography are needed to deal with problems induced by thick resists. Efforts by chip makers, scanner vendors solved the problems in some degree. For example, focus drilling multi-exposure, has improved DOF of some specific layers substantially. But all these approaches have some kinds of issues, such as, throughput losses, etc. As a light source maker, we believe we can make unique contributions to solve the issues. In this report, we are going to show that our advanced Spectral Engineering (SE), a cost-effective way, can provide chip makers with an alternative to cope with the challenges stated above.

Semiconductor demand is steadily growing which is driven by the growth of electronics market used for automobiles to finance, medical to industrial use including agriculture in the last few years. Therefore, the challenges of productivity improvement amongst semiconductor manufacturers are higher than ever. In order to meet that challenge, Gigaphoton has been developed emerging technologies to extend the module replacement interval and reduce the maintenance time along with module life extension. Furthermore, Preventive Maintenance (PM) cycle on the light source is significantly important in order to improve productivity efficiently, that’s why Gigaphoton is focusing to develop technologies for module replacement interval extension not only module base life cycle PM, takes into account PM cycle reduction As implementing new approach for effective PM event managing, Gigaphoton introduced “Availability Maximization(here in afer “AMAX”) as software solution in providing best effective tool utilization aka availability maximization solution to be provided to Semiconductor manufacturer which is operated on FABSCAPE platform. Semiconductor manufacturers are able to create PM planning in terms of both tool availability maximization and scheduled PM which can be aligned to other equipment, fab situation in order to utilize fully productivity in wafer output.

Source optimization (SO) is a widely used resolution enhancement technique to improve the imaging performance of optical lithography systems. Recently, a fast pixelated SO method for inverse lithography has been developed based on the theory of compressive sensing (CS). In last several years, CS has explored numerous reconstruction algorithms to solve for inverse problems. These algorithms are critical in attaining good reconstruction quality also aiming at reducing the time complexity. This paper compares different SO methods based on CS algorithms including the linearized Bregman (LB) algorithm, the alternating direction method of multipliers (ADMM), the fast iterative shrinkage-thresholding algorithm (FISTA), the approximate message-passing (AMP), and the gradient projection for sparse reconstruction (GPSR). Benefiting from the strategy of variable splitting and adaptive step size searching, the GPSR method effectively retains the optimization efficiency. Computational experiments also show that the GPSR method can achieve superior or comparable SO performance on average over other methods. It is also shown that the proposed SO methods can be applied to develop a fast source-mask optimization (SMO) method based on the CS framework.

Multiple patterning ArF immersion lithography has been expected as the promising technology to meet tighter leading edge device requirements. To enhance the resolution and productivity for multiple-patterning application, key light source performances are spectral bandwidth stability and wavelength stability. The increased spectral bandwidth stability contributes to more precise critical dimension (CD) control and improves device yield. The increased wavelength stability can realize accurate focus and improve overlay accuracy. Our new spectral bandwidth control module improves E95 spectral bandwidth stability. The spectral bandwidth has deviations by thermal history with light source operations. It should be always controlled tightly even after a quiescent interval, such as wafer loading. In our laser system, a spectral bandwidth is controlled by adjusting the wavefront of a laser beam using a two-lens optical system within a resonator. A high speed actuator equipped the movable lens enables E95 spectral bandwidth stability to be less variation. New designs of drive mechanism suppress the lens vibration and spectral bandwidth error. This technology enables 3-sigma of E95 spectral bandwidth field average to be under 5 fm. This large shrinkage for E95 spectral bandwidth stability is the key to improve larger focus budgets for a leading edge processes. A new designed line narrowing module (LNM) improves wavelength stability. The wavelength is controlled by changing the rotation of a beam expander prism using actuator. Wavelength stability is improved further by the anti-vibration structure of the actuated prism in the LNM. The new design prism holding mechanisms reduce the mass of actuator load. This increases the stiffness of the system and suppresses the vibration of the prism rotation. New LNM reduce wavelength stability about 20%. The improvement in wavelength stability contributes to accurate focus and overlay. In addition, the lifetime of LNM is extending to reduce the Cost of Operation (CoO) and the light source downtime. A new ArF excimer laser, GT66A, maximizes device yield, process productivity and minimizes the operational costs for chipmakers.

The impacts of aberrations to lithographic metrics, such as defocus, pattern shift and NILS loss, needs to be calculated quickly in numerous applications of the lithography. This paper presents a fast algorithm for calculating these typical lithographic metrics of scanner. Based on the principal component analysis (PCA) of the aberrated lithographic image, the quadratic regression relationship between the principal component (PC) coefficients and Zernike coefficients is established. The quadratic imaging model (QIM) and the gradient information of all PCs are used to calculate the lithographic metrics. Meanwhile, in order to characterize the impacts of spatial varying aberrations on scanning image and the corresponding lithographic metrics, the integral transfer function is used to calculate the PC coefficients of the aberrated scanning image.

Overlay and alignment target recovery process is often required in recording head fabrication where targets are covered by opaque materials. In this study, we have investigated the recovery process impact on the image based overlay (IBO) measurement performance in critical stages of the recording head fabrication. The trench topography created by the target recovery process can result in the asymmetric resist coating uniformity across the wafer and result in errors in the measured overlay values and modeled correctable wafer terms such as the scale and rotation. These errors become significant at critical pattering layers when there is a large z-spacing between the current resist overlay mark and the previous overlay reference mark layer. The recovery pattern size and the recovery depth impact on the measured overlay performance are evaluated. The overlay mark needs to be optimized to reduce the overlay measurement variation. Overlay mark designs, including box-in-box, AIMid and multi AIMid overlay marks, are investigated. Self-referencing marks (SRM) are used to evaluate recovery process and overlay mark impacts on overlay measurement accuracy.

A proof-of-concept Krypton Fluoride excimer laser-based patterning system was designed and constructed with dual applications in lithography and laser-ablation patterning. For the lithographic patterning application, utilizing a typical positive-tone chemical amplification resist material, potential for sub-μm patterning was realized with ultimate resolution obtained at 0.8μm 1:1 lines-and-spaces (L/S). Moreover, extremely large depth-of-focus was confirmed, e.g. 50μm at 5μm 1:1 L/S. For the laser-ablation patterning application, ultimate resolutions of up to 1.2μm 1:1 L/S were obtained using a novolac-based material. It was also understood that higher exposure energy per shot can aid in pattern profile enhancement. Results obtained here show the potential of the patterning system for μm and sub-μm level patterning of thick resist films.

Over the past few years, patterning edge placement error (EPE) has been established as the key metric for patterning budget generation. In previous work [1] it has been shown that local variability of contact within 28nm node SRAM regular array accounts for more than 90% of total variability. Among the most obvious source of local variability, we can think of optical proximity correction (OPC), mask process, wafer process (litho and etch). If one would like to make breakdown between these sources, process related sources will be very measurement consuming to characterize, and even more complex to correct. On the opposite, OPC can be characterized computationally as well as corrected. Therefore, this paper proposes a computational method to evaluate and correct pattern variability induced by OPC within regular array layout. In a different field of application, array of pixels in imager SoC is very sensitive to pattern variability, especially when it is periodic. This is known as MURA effect, and many works have shown this effect in the field of flat panel display [2]. The challenge is similar in the field of image SoC. Once again, OPC variability is also a contributor to this effect. Therefore, array of pixels is also benefitting from the method proposed in this paper.