Since its introduction more than a decade ago, inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography. Numerous studies have demonstrated that curvilinear ILT mask shapes produce the best process window. However, the runtimes associated with this computational technique have limited its practical application. In 2019, D2S introduced an entirely new, stitchless approach for ILT . This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. The masks used to validate wafer results for this system were written by a multi-beam mask writer. The question remained of whether it was possible to use this new approach to ILT in a way that could be written by a variable-shaped beam (VSB) mask writer. This paper introduces a new method, in which a process called mask-wafer cooptimization (MWCO) is performed during ILT optimization. This new approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within reasonable write times. It shortens the total turnaround time so that VSB mask writers can produce full-chip, curvilinear ILT masks within a practical, 12-hour time frame, while also producing the largest process windows. It should be noted that this enables curvilinear or any-angle targets for the wafer design to be processed by curvilinear ILT and then written by VSB mask writers for 193i processes. While MWCO as a concept can be used for multi-beam mask writers as well, this paper is focused on MWCO for VSB mask writers.