This PDF file contains the front matter associated with SPIE Proceedings Volume 11328, including the title page, copyright information, table of contents, and author and conference committee lists.

As the litho hotspot detection runtime is currently in a continuous increase with sub-10nm technology nodes due to the increase of the design and process complexity, new methods and approaches are needed to improve the runtime while guaranteeing high accuracy rate. Machine-Learning Fast LFD (ML-FLFD) is a new flow that uses a specialized machine learning technique to provide fast and accurate litho hotspot detection. This methodology is based on having input data to train the machine learning model during the model preparation phase. Current ML-FLFD techniques depend on collecting hotspots (HS) and Non hotspots (NHS) data from the drawn layer in order to train the model. In this paper, we present a new technique where we use the retarget data to train the machine learning model instead of using the drawn hotspot data. Using retargeting data is getting one step closer to the actual printed contours which gives a better insight about the hotspots of the manufactured wires during the machine learning model training step. The effect of using closer data to the printed contours will be reflected on both the accuracy and the extra rate which will reduce simulation area. In the different sections of this paper, we will compare the new approach of using retarget data as a ML input to the current technique of using drawn data. Pros and cons of the two approaches will be listed in details including the experimental results of hotspot accuracy and litho simulation area.

Design rule for advanced logic node is optimized together with EUV NXE 3400 wafer data and OPC performance. Imaging parameters such as SMO source, dose sensitivity, MEEF and other are considered in defining the pattern fidelity and associated design rules. In addition, positive tone development (PTD) process employing Dark Field (DF) EUV mask and negative tone development (NTD) process using Bright Field (BF) mask are included in the scope. Key differences between PTD and NTD process will be discussed from the perspective of fundamental imaging, OPC and lithography process. At last, stochastic effect will be evaluated on the key design rules such as tip- to-tip, tip-to-line, width/space etc.

As feature resolution and process variations continue to shrink for new nodes of both DUV and EUV lithography, the density and number of devices on advanced semiconductor masks continue to increase rapidly. These advances cause significantly increased pressure on the accuracy and efficiency of OPC and assist feature (AF) optimization methods for each subsequent process technology. Several publications and industry presentations have discussed the use of neural networks or other machine learning techniques to provide improvements in efficiency for OPC main feature optimization or AF placement. In this paper, we present results of a method for using machine-learning to predict OPC mask segment displacements. We will review several detailed examples showing the accuracy and overall OPC TAT benefits of our method for advanced node manufacturing test cases. We will also discuss the experiments testing the amount and diversity of training data required to achieve true production level OPC stability.

Memory cells and access structures consume a large percentage of area in embedded devices so there is a high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. As the scaling drives lithography even deeper into the low-k1 regime, cooptimization of design layout, mask, and lithography is critical to deliver a production-worthy patterning solution. Computational lithography like Inverse Lithography Technology (ILT) has demonstrated it is an enabling technology to derive improved solutions over traditional OPC as reported in multiple prior publications. In this paper, we will present results of a study on advanced memory cell design optimization with Cell-Level ILT (CL-ILT) where significant design hierarchy can be retained during ILT optimization. Large numbers of cell design variations are explored with automatically generated patterns from ProteusTM Test Pattern Generator (TPG). Fully automated flows from pattern generation to mask synthesis with ILT, data analysis and results visualization are built on ProteusTM Work Flow (PWF) for exploring a fully parameterized design space of interest. Mask complexity including assist features (AF) types, rule or model based, and main feature segmentation are also studied to understand the impact on wafer lithographic performance. A heatmap view of results generated from this design exploration provides a clear and intuitive way to identify maximum design limits of memory cells. Comparison of results from ILT and traditional OPC will be presented as well with both wafer and simulation data.

N2 node is introduced at 42nm poly pitch (CPP), 16 metal pitch (MP) by using 5 tracks (5T) cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction, the patterning of the middle of line (MOL) become challenging. In this paper, two contact patterning schemes, staggered and aligned are presented and evaluated in terms of their impact on electrical performance on FinFET and Nanosheet. Simulations show that both options meet the performance target for N2. However, scaling at these dimensions also challenges the p-n separation between devices in a logic cell, which results in area penalty in complex cells. A novel device is introduced at N2 node, Forksheet, which shows higher performance and better area scaling at standard cell level compared to FinFET and NanoSheet.

At the core of Design-technology co-optimization (DTCO) processes, is the Design Space Exploration (DSE), where different design schemes and patterns are systematically analyzed and design rules and processes are co-optimized for optimal yield and performance before real products are designed. Synthetic layout generation offers a solution. With rules-based synthetic layout generation, engineers design rules to generate realistic layout they will later see in real product designs. This paper shows two approaches to generating full coverage of the design space and providing contextual layout. One approach relies on Monte Carlo methods and the other depends on combining systematic and random methods to core patterns and their contextual layout. Also, in this paper we present a hierarchical classification system that catalogs layouts based on pattern commonality. The hierarchical classification is based on a novel algorithm of creating a genealogical tree of all the patterns in the design space.

In this paper, we propose methodologies used in a software system for checking process friendliness (including lithography friendliness) and routability (including pin accessibility) of standard cells. In the process of designing physical layouts of standard cells, it is essential to consider their process friendliness since specific cells have very high tendencies to create process weakpoints (which include lithography hotspots) after their instances are placed and routed. On the other hand, at advanced process nodes, the routability of standard cells must also be considered since there are combined trends of increasing pin densities and increasing design rule complexities. Experimental results show that our software system is able to effectively detect problematic standard cells which have critical process friendliness and/or routability issues.

As traditional pitch scaling is losing steam, 3D logic is being explored to further extend density scaling as an alternative to continued standard cell scaling. This paper will discuss standard cell architectures to be used in a Sequential 3D process where the SoC is comprised out of 2 or more tiers of active CMOS with a given BEOL metal stack per tier. Using backside interconnect metals as standard cell power rails, a smart partitioning of the metal usage within standard cells can be obtained leading to 4 track cell height scaling. A design abstraction using crenelated design is however needed at block level to mitigate via and metal line end conflicts.

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.

An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices and their integration into functional logic cells, the time consuming task of generating and validating a process design kit (PDK) for each technology definition is eliminated by taking advantage of automated standard cell generation and direct emulation-based parasitic extraction. Further efficiency gains are obtained through a customized flow that allows a large number of place and route (PnR) experiments to be executed automatically. The efficiency of the presented Pathfinding DTCO flow is demonstrated in experiments quantifying block-level PPA changes in different implementations of finFET and CFET devices.

With multi patterning being the method of choice for pushing technology further down the shrink roadmap, new design weak points are emerging that have multi-layer components and are difficult to find and to define. On the other hand, advanced OPC methodologies like retargeting and recentering help alleviate many of the occurrences, leaving only a few locations that are critical and need to be dealt with in design. State of the art in-design weak point auto fixing is usually done by identifying a weak point by a pattern match, and providing the router either a “safe” alternative configuration or tell it to reroute locally, also called rip-and-reroute. The dilemma for developing pattern matching decks that are used in place and route tools is that one cannot be too specific in the pattern definition as there will be escapes that can possibly cause problems in the fab. Having a more general pattern definition will prevent escapes, but will flag many locations that don’t really require fixing. As a consequence, this more general pattern definition may bog down the place and route tool and can actually result in area bloat if too many rip-and-reroute areas are identified. We have come up with a patented flow that allows very specific weak point detection with a low escape rate. The flow starts with a generic pattern definition of the fail mode, but reduces the number of occurrences by identifying safe configurations. Usually, the pattern extent of the safe configuration is larger than the initial generic pattern, and may contain more layers. Any known safe configuration is added to a “good pattern” database which is then subtracted from the initial pattern match. Thus, the number of design locations that need to be auto fixed is kept at a minimum. As the technology matures, more safe patterns are found and added to the database, thus reducing the amount of auto fixing required.

As feature sizes diminish and correction flow complexity increases, it becomes extremely difficult to create homogeneous mask synthesis correction recipes that can pass lithographic verification without some failing hotspots. When encountered in the production line, these areas are frequently fixed quickly so the tapeout can resume and time-tomask is preserved as much as possible. However, these hotspots may occur in future designs, so it is beneficial to update the standard correction recipe with this hotspot information and avoid verification failures before they occur. This paper examines inserting unique hotspot corrections into the standard correction flow using pattern matching to identify the hotspot areas. Standard correction recipes can be updated to accept these hotspot areas and adjust recipe parameters or correction techniques in a standard manner so that these hotspots will be fixed automatically. This automation technique minimizes human interaction with the recipe.

In this paper, we are proposing different techniques to enhance the printability of 2D shapes at 3nm node of Block/Cut shapes in self-Aligned Multi-patterning approaches. Multiple directions such as OPC optimization, fragmentation optimization, tagging, optimization of 2D shapes dimensions, controlling the direction of movement of OPC mask edges, using skew edges and more approaches are used to meet the printability specs of 3 nm node. In addition, a complete study to define the best dimensions to 2D junction of block/cut shape and its distance from metal line has been conducted. The results are evaluated based on the resulted EPE and PVBand. We managed to reach EPE< 1nm and PVBand < 3nm (IMEC specs at 3nm node).

Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle, in turn saving time and efforts. In this paper, we describe a new bottom-up approach to layout risk assessment that can rapidly identify unique patterns in layouts, and in combination with techniques like feature filters, location mapping and clustering, can pre-determine their criticality. A massive highly performant pattern database of single and multilayer patterns, along with their features and locations, forms the core of the system. While pattern analyses may be pertaining to the short range of design space, silicon defects and simulations extend to a much larger scope. Therefore, the database is extended to defect data extracted from Silicon inspection tools like Bright Field Inspection (BFI) and Scanning Electron Microscopy (SEM). When stored in an optimized manner, it can aid fast and efficient large data analysis and machine learning within critical tapeout review time which is typically a few days. Machine learning combined with design feature filters can then be used for anomaly detection and failure prediction at layout, layer and pattern levels. As a result, outlier patterns can be visually reviewed and flagged for custom targeted simulations and silicon inspection. Further, adding new layout patterns to the pattern database will make it possible to repeat this exercise for subsequent new layouts.

Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a set of new rules to detect high risk design layout patterns. The proposed methods improve design margins while avoiding area overhead and complex design restrictions. In addition, the proposed method introduces an in-design pattern replacement with automatically generated fixing hints to improve all matched locations with identified patterns.

Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.

A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.

Computational technologies are still in the course of development for nanoimprint lithography (NIL). Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. In this paper, we introduce a new process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the positions of the droplets and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented here.

As one of Resolution Enhancement Techniques, a mask optimization such as Pixel-based Optical Proximity Correction or Inverse Lithography Technology is well discussed. In this paper, a pixel-based mask optimization using 0-1 Quadratic Programming problem (0-1 QP) is proposed to obtain enough image contour fidelity and tolerance to process variation in a short time. By formulating 0-1 QP to maximize intensity slope around between edges of target patterns, suppression of image contour distortion by the process variation is realized. The defined 0-1 QP is relaxed into Lagrangian relaxation problem and an approximate solution of the defined 0-1 QP is obtained by solving Lagrangian relaxation problem by using Subgradient method and gradient deciding method. Moreover, by applying a correction method which corrects boundary pixel of target patterns precisely into the mask obtained by 0-1 QP, enough shape fidelity toward target patterns can be obtained.

CMOS technology scaling is enabled by multiple logic transistor architecture change from Planner to FinFET to Nanosheet and most recently Forksheet and CFET. Every architecture change has significant impact on the power-performance-area (PPA) scaling of any system on chip (SOC). A comprehensive Design-Technology-optimization (DTCO) methodology is needed to analyze this impact. In this paper technology scaling impact of this architecture change along with lithographic scaling will be analyzed from standard Cell to Block Level Place-Route to realize realistic PPA estimate.

Fully depleted silicon on insulator (FDSOI) circuits provides unique advantages of being of low power, or high performance, or a combination of both if properly deployed. The tradeoff is that designers need to take steps to ensure interference between circuit blocks of different voltage domains, and antenna damages do not occur. This paper describes an efficient design, which combines guard rings and antenna diodes into one, to resolve these potential issues.

Current Wafer-to-Wafer hybrid bonding process technology allows die stacking with 3D structure pitches in range of 1μm. Independent wafer processing prior to 3D stacking enables heterogeneous CMOS process integration, where each wafer FEOL, BEOL can be optimized for a given functionality to trade-off system performance and cost. Typical functional system partitioning aims the split of the system memory from the logic. While 3D structures with coarser pitches (e.g. micro-bumps) are already used to split the last-level cache (LLC) from the rest of the system (e.g. HBMs), finer 3D structures can be used to split lower and intermediate cache memory layers (L2, L1) from the core logic. System performance gets better since delay and cache latency can be reduced. Also the system cost can be reduced, since only the core layer is now built using the most expensive CMOS process. In this article we quantify the system-level post place and route performance and area benefits of Memory-on-Logic applications using advanced CMOS processes (< 10nm) for various BEOL configuration options, i.e. the number and geometrical properties of different metal layers used in the BEOL stack.

For over ten years, lithographers have been attempting to use ILT to maximize the wafer process window. Only recently has the ability been available to manufacture the curvilinear ILT reticles. It has recently been shown that migrating the mask data to a purely curvilinear path (avoiding Manhattanization after ILT output) maximizes wafer process yield by minimizing mask variability. Therefore, the last two steps of the design+manufacturing flow can be done in a completely curvilinear way. It is now time to extend these ideas to design itself. It has been demonstrated earlier that these designs can reduce the number masks needed for a device. We will show the ability to achieve better device behavior by requesting more manufacturable shapes. As part of this we will suggest how to update the existing Manhattan design rule check (DRC) rules with curvilinear ones.

The edge placement error (EPE) of a 5nm node SRAM is examined in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization, and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matcher error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Tradeoffs can be made to sacrifice EPE from one EPE component because another EPE component cannot be reduced further. Since SEPE is difficult to reduce, overlay EPE is sacrificed to reduce the total EPE. The ways to reduce overlay EPE in manufacturing include mark optimization to minimize effect of odd Zernike aberrations, minimization of the effect of process mark deformation on the alignment measurement, and minimization of wafer deformation through scanner stage and projection optics correction.

As the semiconductor industry strives to keep Moore’s Law moving forward, companies are continually confronted with new and mounting challenges. The use of fin field-effect transistors (finFETs) and the recent introduction of gate-allaround (GAA) finFETs present questions of performance, scalability, and variation resilience that have yet to be fully resolved. The need for multi-patterning, which has been in place since the 22 nm node, is not going away, even with the introduction of extreme ultraviolet (EUV) lithography. Complex fill requirements have emerged as a critical success factor in both manufacturability and performance in leading-edge nodes. These factors, among others, have created significant impacts across the electronic design automation (EDA) design-to-tapeout ecosystem, particularly in physical verification. In response, EDA suppliers constantly evaluate and experiment with the design information they receive from both design houses and foundries, and often establish collaborative projects, to assess the impact of changing technology, and to develop and implement new functionality and new tools that reduce or eliminate time and resource impacts while ensuring accuracy and full coverage. Replacing inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality helps maintain, and even grow, both the bottom line and product quality in the face of increasing technological complexity.

Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.

The stability of photolithography process tool is the fundamental to the fabrication of semiconductor devices. Several process control methods are employed to qualify and then monitor every single process layer at the photolithography stage. The CDSEM (Critical Dimension Scanning Electron Microscope) measurements on metrology features and the optical inspection and DRSEM (Defect Review Scanning Electron Microscope) on device features for Process Window Qualification is part of the conventional process control. Here we employed a novel PSD (Process Stability Diagnosis) solution that provides detailed Bossung plot like analysis on device features using CDSEM or DRSEM images. This provides quick insight into the process behavior and also identifies the root cause for any deviation. In this paper we will discuss about monitoring the depth of focus and the best focus as well as diagnosis for lens parameters like astigmatism and spherical aberration. We describe the method of extracting relevant parameters from high resolution images and establishing an automatic monitor for these critical indicators.

Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.

Silicon weak pattern exploration becomes more and more attractive for yield improvement and design robustness as these proven silicon weak patterns or hotspots directly reveals process weakness and should be avoided to occur on the chip design. At the very beginning, only a few known hotspot patterns are available as seeds to initialize the weak pattern accumulation process. Machine learning technique can be utilized to expand the weak pattern database, the data volume is critical for machine learning. Fuzzy patterns are built and more potential hotspots locations are found and sent to YE team to confirm, thus more silicon proven data is available for machine learning model training, both good patterns and bad patterns are valuable for the training data set. The trained machine learning model is then used for new hotspots prediction. The outcome from the machine learning prediction need to be validated by silicon data in the first few iterations. When a reliable machine learning model is ready for hotspots detection, designers can run hotspot prediction at the design stage. There are some techniques in training the mode and will be discussed in details in the paper.

High yield is always demanded in IC manufacturing, however, as process variations and random particles are part of the manufacturing process in nature, yield and circuit performance are inevitably impacted by these factors especially in advanced nodes. Even so, there’s often some room to polish designs to be manufacturing friendly. The design for manufacturability (DFM) approach has been taken to optimize designs to minimize process variation impact on the yield and performance. One area gaining success toward yield improvement is VIA (Vertical Interconnect Access) design optimization. There are some technical approaches that designers may take: adding redundant VIA at possible spots without increasing the design area is a proven way to address random particle induced VIA void issues; increasing VIA enclosure area by shifting VIA to an optimum location effectively minimizes masks misalignment induced enclosure issues, and note that shifting VIA needs to consider some complex situations when clustered VIAs constrain each other. There are also other circumstances that need to be considered and handled depending on specific manufacturing process. All these contents will be presented in detail in the paper.

As we move to more advanced nodes, the number of Chemical Mechanical Polishing (CMP) steps in semiconductor processing is increasing rapidly. CMP is known to suffer from pattern dependent variation such as dishing, erosion, recess, etc., all of which can cause performance and yield issues. One such yield issue seen in back end of line (BEOL) Cu interconnect CMP processes is pooling. Pooling exists when there is uncleared bulk Cu and/or barrier residue remaining after final CMP step, leading to shorts between neighboring interconnect lines. To detect potential pooling locations on a given design, for a given CMP process, predictive CMP models are needed. Such models can also aid in CMP process and chip design optimizations. In this paper we discuss how a pattern dependent CMP effect that we call the “local neighborhood effect” causes large recesses that can lead to pooling in Cu interconnect CMP processes. We also discuss modeling this effect as part of an advanced predictive CMP modeling system and show how the resulting modeling system accurately predicts Cu pooling on several 14 nm designs.

Chemical-mechanical polishing (CMP) is a key process in integrated circuit (IC) manufacturing. Successful fabrication of semiconductor devices is highly dependent on the final planarity of the processed layers. Post-CMP topography variation may cause degradation of the circuit performance. Moreover, the depth-of-focus (DOF) requirement is critical for lithography of subsequent layers. As such, planarity requirements are critical for maintaining IC manufacturing technology scaling trends, and supporting device innovation. To mitigate post-CMP planarity issues, dummy fill insertion has become a commonly-used technique. Many factors impact dummy fill insertion results, including fill shapes, sizes, and the spacing between both fill shapes and the drawn layout patterns. The goal of the CMP engineer is to optimize design planarity, but the variety of fill options means just verifying the design rules for fill is a challenging task. This data collection currently requires a long development cycle, consuming a great deal of time and resources. In this paper, we show how CMP modeling can help resolve these issues by applying CMP modeling and simulations to drive Calibre YieldEnhancer SmartFill parameters that have been optimized for dummy fill. Additional capabilities in the SmartFill functionality automate CMP hotspot fixing steps. Using CMP simulations, engineers can get feedback about post-CMP planarity for given fill options in a much shorter time. Not only does this move dummy fill optimization experiments from a real lab into a virtual lab of CMP modeling and simulation, but it also provides more time for these experiments, providing improved results.

It’s desirable to gain high yield and good performance for memory products. Designers have to do some advanced DFM checking on their designs and fix all the critical design issues to be correct by construction before manufacturing. One of the DFM checking items is the litho hotspot checking, LFD (Litho Friendly Design) is the tool adopted for that checking due to its user friendly interface for designers and being able to be integrated with other tools for the advanced checking flow development. One challenge to enable this checking as the signoff item is the long runtime due to the computing-intensive litho simulation. Multiple ways have been figured out to reduce the runtime, for instance, hierarchical checking flow similar to hierarchical design flow under the assumption that many design blocks are reused on the top level; simulation only on the area selected by weak pattern candidates stored in a pattern matching library; simulation only on the unique pattern area by firstly decomposing the layout. All these approaches always tradeoff between runtime and simulation accuracy and come to use with different expectations as the process gradually matures. This paper introduces another technique to reduce the simulation time. This technique is essentially a pattern matching extended application and will be introduced in detail in the paper.

In the advanced nodes, abutted corners often referred to as kissing corners, are not physically printable using single layer photolithography techniques. In order to mitigate any downstream impact, the authors propose specific kissing corner handling methodologies in Mask Data Prep (MDP). In the layout, beveling is a method that can add or subtract shapes to either allow a resist feature to remain or space to resolve. Unlike functional active areas, Fill kissing corners can be proactively avoided by a correct-by-construction approach. Both these methodologies yield faster processing while improving the results without necessitating any design rule change.

As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc) process chemical (NTD) and Control Algorithm (Focus APC) into the mature tech nodes such as 14nm/12nm, more process window and less process variations are expected for latecomer wafer fabs (Tier-2/3 companies) who just started the competition with Tier-1 companies. With improved weapons, latecomer companies are able to review their DFM strategy one more time to see whether the benefit from hardware/process/control algorithm improvement can be shared with designers In this paper, we use OPC simulation tools from different EDA suppliers to see the feasibility of transferring the benefits of hardware/process/control algorithm improvement to more relaxed design limitation through source mask optimization (SMO): 1) Better hardware: scanner (better focus/exposure variation), CMP (intrafield topo), Mask CD variation (relaxed MEEF spec), etc.; 2) New process: from positive tone development to negative tone development; 3) Better control schemes: holistic focus feedback, feedback/forward overlay control, high order CD uniformity improvement; Simulations show all those gains in hardware and process can be transferred into more relaxed design such as sub design rule structure process window include forbidden pitches (1D) and smaller E2E gaps (2D weak points).

In urgent post tape-out, runtime is a big challenging for backend layers’ OPC (Optical Proximity Correction). Sometimes there is no extra time for OPC to clean all the ORC (Optical Rule Check) hotspots with recipe tuning. So the repair flow is the good choice, the repair flow is costly final step, especially for Metal layer’s. In some challenging case, there will be thousands or millions hotspots which can’t pass various ORC criteria need to be into repair flow, thus not only makes our system overloading and the runtime is unacceptable. There are many applications for Machine Learning (ML) in IC field, such as ML-OPC, ML-Hotspot detection and ML-SRAF etc. And Calibre ML-OPC has powerful functionality which fits the requirement of repair flow very well. In this paper, we will introduce how to use Calibre ML-OPC to reduce the most of the defects to speed up the repair process and demonstrate the benefit comparing to the traditional repair flow.

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.

As feature resolution and process variations continue to shrink for new nodes of both DUV and EUV lithography, the density and number of devices on advanced semiconductor masks continue to increase rapidly. These advances cause significantly increased pressure on the accuracy and efficiency of OPC and assist feature (AF) optimization methods for each subsequent process technology. To meet manufacturing yield requirements, significant wafer retargeting from the original design target is often performed before OPC to account for both lithographic limitations and etch effects. As retargeting becomes more complex and important, rule-table based approaches become ineffective. Alternatively, modelbased optimization approaches using advanced solvers, e.g., inverse lithography technology (ILT), have demonstrated process window improvement over rule-based approaches. However, model-based target optimization is computationally expensive which typically limits its use to smaller areas like hotspot repairs. In this paper, we present results of a method that uses machine-learning (ML) to predict optimal retargeting for line-space layers. In this method, we run ILT co-optimization of the wafer target and process window to generate the training data used to train a machine learning model to predict the optimum wafer target. We explore methods to avoid ML model overfitting and show the ML infrastructure used to integrate ML solution into a manufacturable OPC flow. Both lithographic quality and runtime performance are evaluated for an ML enabled retargeting flow, an ILT flow and a simple rule table flow at advanced node test cases.

As VLSI device feature sizes are getting smaller and smaller, lithography hotspot detection and elimination have become more important to avoid yield loss. Although various machine learning based methods have been proposed, it is not easy to find appropriate parameters to achieve high accuracy. This paper proposes a feature selection method by using the probability distributions of layout features. Our method enables automatic feature optimization and classifier construction. It can be adaptive to different layout patterns with various features. In order to evaluate hotspot detection methods in the situation close to actual problem, dataset based on ICCAD2019 dataset is used for evaluation. Experimental results show the effectiveness of our method and limitations.

As we are stepping towards sub-10 nm nodes, process window monitoring for systematic defects is becoming more and more critical. In traditional process window excursion and control (PWEC) methods often optical defect inspection is done on a focus and dose modulated wafer first. Once the different systematic defects are detected in a particular focus/energy die, we flag the repeating defect locations as potential hotspots and rank them based on how early/late they fail in a focus/energy modulated columns. So, during this first pass we get a rough idea of which locations are failing. However, due to limited resolution of optical tools, the true process window can only be gathered during a second pass with an ebeam tool. The key idea to define a true process window demands a detailed analysis of CD and other underlying features. We have proposed a new method of analyzing the process window with an unsupervised machine learning approach. Our proposed algorithm will extract the underlying key features and encode these to latent feature vectors or latent vector space instead of the conventional CD, given a dataset of thousands of CD-SEM images, and then rank the images based on a similarity index and then to automatically determine the process window. This work addresses the following problems (1) with a defect inspection tool this task seems tedious and time consuming and often require human intervention to analyze a large number of features, (2) a CD-SEM based process window analysis might not always match with a defect inspectionbased process window. Our generalized variational auto-encoder based approach does this automatically. Also, we have analyzed and validated our result against conventional approach.