DTCO acceleration to fight scaling stagnation

Lars Liebmann; Daniel Chanemougame; Peter Churchill; Jonathan Cobb; Chia-Tung Ho; Victor Moroz; Jeffrey Smith

doi:10.1117/12.2554025

23 March 2020 DTCO acceleration to fight scaling stagnation

Lars Liebmann, Daniel Chanemougame, Peter Churchill, Jonathan Cobb, Chia-Tung Ho, Victor Moroz, Jeffrey Smith

Proceedings Volume 11328, Design-Process-Technology Co-optimization for Manufacturability XIV; 113280C (2020) https://doi.org/10.1117/12.2554025
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices and their integration into functional logic cells, the time consuming task of generating and validating a process design kit (PDK) for each technology definition is eliminated by taking advantage of automated standard cell generation and direct emulation-based parasitic extraction. Further efficiency gains are obtained through a customized flow that allows a large number of place and route (PnR) experiments to be executed automatically. The efficiency of the presented Pathfinding DTCO flow is demonstrated in experiments quantifying block-level PPA changes in different implementations of finFET and CFET devices.

Conference Presentation

Citation Download Citation

Lars Liebmann, Daniel Chanemougame, Peter Churchill, Jonathan Cobb, Chia-Tung Ho, Victor Moroz, and Jeffrey Smith "DTCO acceleration to fight scaling stagnation", Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280C (23 March 2020); https://doi.org/10.1117/12.2554025

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