Holistic method for reducing overlay error at the 5nm node and beyond

Robert Socha

doi:10.1117/12.2554799

25 March 2020 Holistic method for reducing overlay error at the 5nm node and beyond

Robert Socha

Proceedings Volume 11328, Design-Process-Technology Co-optimization for Manufacturability XIV; 113280V (2020) https://doi.org/10.1117/12.2554799
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

The edge placement error (EPE) of a 5nm node SRAM is examined in detail for aligning a via 0 (V0) layer to the metal 0 (M0) layer. These layers are optimized with source mask optimization, and the EPE is minimized from stochastics, global critical dimension uniformity (CDU), overlay, optical proximity correction (OPC) error, and scanner matcher error. The largest source of error in EPE is from stochastic EPE (SEPE) in which 5nm of maximum EPE is produced. Tradeoffs can be made to sacrifice EPE from one EPE component because another EPE component cannot be reduced further. Since SEPE is difficult to reduce, overlay EPE is sacrificed to reduce the total EPE. The ways to reduce overlay EPE in manufacturing include mark optimization to minimize effect of odd Zernike aberrations, minimization of the effect of process mark deformation on the alignment measurement, and minimization of wafer deformation through scanner stage and projection optics correction.

Citation Download Citation

Robert Socha "Holistic method for reducing overlay error at the 5nm node and beyond", Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280V (25 March 2020); https://doi.org/10.1117/12.2554799

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