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23 March 2020 VIA design optimization for fast yield ramping in advanced nodes
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Abstract
High yield is always demanded in IC manufacturing, however, as process variations and random particles are part of the manufacturing process in nature, yield and circuit performance are inevitably impacted by these factors especially in advanced nodes. Even so, there’s often some room to polish designs to be manufacturing friendly. The design for manufacturability (DFM) approach has been taken to optimize designs to minimize process variation impact on the yield and performance. One area gaining success toward yield improvement is VIA (Vertical Interconnect Access) design optimization. There are some technical approaches that designers may take: adding redundant VIA at possible spots without increasing the design area is a proven way to address random particle induced VIA void issues; increasing VIA enclosure area by shifting VIA to an optimum location effectively minimizes masks misalignment induced enclosure issues, and note that shifting VIA needs to consider some complex situations when clustered VIAs constrain each other. There are also other circumstances that need to be considered and handled depending on specific manufacturing process. All these contents will be presented in detail in the paper.
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Min Wang, Yizhong Zhang, Shirui Yu, Xinyi Hu, Qijian Wan, Zhengfang Liu, Zhixi Chen, and Chunshan Du "VIA design optimization for fast yield ramping in advanced nodes", Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132814 (23 March 2020); https://doi.org/10.1117/12.2551683
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