InP/Low-Temperature-Deposited SiO2 Interface

P. D. Gardner; S. Y. Narayan

doi:10.1117/12.962001

28 November 1989 InP/Low-Temperature-Deposited SiO₂ Interface

P. D. Gardner, S. Y. Narayan

Proceedings Volume 1144, 1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices; (1989) https://doi.org/10.1117/12.962001
Event: First International Conference on Indium Phosphide and Related Material for Advanced Electronic and Optical Devices, 1989, Norman, OK, United States

Abstract

This paper describes the characteristics of the InP/low-temperature-deposited SiO2 MIS system, with emphasis on C-V hysteresis and drain current drift in InP MISFETs. The SiO2 was deposited using a low-pressure (2 Torr) Hg-assisted UV deposition system using SiH4 and N20 as source gases. Depositions were carried out at substrate temperatures of 75°C to 170°C. MIS capacitors, fabricated on n-epi/n+-InP substrates (to minimize series resistance) with Al or Ti/Pt/Au metallizations were characterized using C-V measurements. We show that long-term (16 h 300°C in H2) anneals reduces interface state density (Dit), oxide fixed charge, and C-V hysteresis. Dit values of < 1x10¹¹ cm-2eV-1, adequate for good MISFET operation, were routinely obtained over a large portion of the bandgap. InP MISFETs with 1-μm gatelength fabricated with this oxide showed good performance at 20 GHz. C-V measurements with only positive and only negative voltage sweeps showed C-V hysteresis to be a function of both the magnitude and sign of the bias voltage. Positive bias had the largest effect (n-type capacitors). This suggests that both electron- and hole-trapping occur. C-V measurements at 300 K and 77 K show C-V hysteresis to be independent of temperature, suggesting that a mechanism such as tunneling may be responsible. Short- (100 μs) and long-term (10³s) drain-current drift measurements made on ion-implanted, self-aligned-gate InP MISFETs showed drifts of ~ 5%.

Citation Download Citation

P. D. Gardner and S. Y. Narayan "InP/Low-Temperature-Deposited SiO₂ Interface", Proc. SPIE 1144, 1st Intl Conf on Indium Phosphide and Related Materials for Advanced Electronic and Optical Devices, (28 November 1989); https://doi.org/10.1117/12.962001

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