Exact computations, performed with residues, occur in Number Theoretic Transforms and Residue Number System implementations. Once thought awkward to implement with standard logic circuits, the application of efficient small lookup tables, constructed with pipelined dynamic ROM's, allows very efficient construction of hardware ideally suited to residue operations. Linear DSP operations that are compute bound (require many arithmetic computations per input/output sample), are best suited for implementation with systolic arrays. For very high throughput operations, bit-level systolic arrays appear to be ideally suited to their implementation. The dynamic ROM's used for the residue computations, are a perfect vehicle for implementing such operations at the bit-level in a systolic architecture. This paper discusses VLSI architectures based on finite ring computations, using linear systolic arrays of small look-up tables.The advantage of this approach is that fixed coefficient multiplication requires no in crease in hardware over that required for general addition, and the resulting structure is homogeneous in that only one cell type is required to implement all of the processing functions. Several advantages accrue in the VLSI setting, particularly clock rate increase, ease of testability and natural fault tolerance Three different approaches to implementing the finite ring/field residue calculations are discussed. The first uses a bit-level steering mechanism around small dynamic ROM's; two applications of this technique to digital signal processing are outlined. The other two techniques are based on a redundant binary representation implemented with a pipelined adder configuration, and an iterative solution technique based on neural-like networks.