Implementing A 64kbit/s Video Codec On DSP Hardware

Luis de Sa; Victor Silva

doi:10.1117/12.962312

30 January 1990 Implementing A 64kbit/s Video Codec On DSP Hardware

Luis de Sa, Victor Silva

Proceedings Volume 1153, Applications of Digital Image Processing XII; (1990) https://doi.org/10.1117/12.962312
Event: 33rd Annual Technical Symposium, 1989, San Diego, United States

Abstract

A modular hardware architecture for video coding at p x 64kbit/s data rates is described. The codec uses several digital signal processors (DSPs) and can be viewed as a single instruction multiple data (SIMD) computing architecture. Every image in a sequence is divided in regions of horizontal strips and each region is operated by its an processor. These local processors communicate with a central processor which codes (decodes) the cosine transformed frame differences. Lateral communication between adjacent processors is also permitted. This is done by memory sharing and allows comparisons between blocks situated in neighbouring regions, as required by most motion estimation algorithms. The codec is built using the modern TMS320C30 digital signal processor. The number of processors used in both the coder and the decoder depends on the application. This is a consequence of the modular design and allays the machine to be configured to suit a particular algorithm complexity or a desired quality of the coded image.

Citation Download Citation

Luis de Sa and Victor Silva "Implementing A 64kbit/s Video Codec On DSP Hardware", Proc. SPIE 1153, Applications of Digital Image Processing XII, (30 January 1990); https://doi.org/10.1117/12.962312

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