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In our paper we will extend the previously introduced “Excursion Prevention” concept for CDU improvement [1] toward the reduction of Edge Placement Errors by additionally correcting intrafield overlay errors using the ZEISS ForTune system for a critical 22nm contact to gate application. We will discuss EPE budget and compare intra-field, inter-field and local variations. In particular, it will be shown how the interaction of remaining systematic intra- and inter-field errors can create local EPE hotspots that are prone to result in patterning failures. By convoluting these systematic EPE errors with random across wafer and local EPE errors, we will predict patterning failure maps across wafer, where the EPE hotspots manifest in local failures and thus yield stripes. Finally we will discuss how the reduction of intra-field overlay and CDU by using ForTune mask tuning is able to dramatically reduce the EPE hotspots and thus helps to prevent pattering failure and yield striping. [1] Rolf Seltmann*a, Aravind Narayana Samyb, Thomas Thammb, Ofir Sharonic, Yael Sufrinc, Avi Cohenc, Thomas Scherueblc : Improving Chip Performance by Photomask Tuning: Ultimate intra-field CD control as a major part of an overall excursion prevention strategy, Proc. SPIE. 11148, Photomask Technology 2019
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