To keep up with logic area scaling, BEOL dimensions have been reduced at an accelerated pace, leading to ever smaller metal pitches and reduced cross-sectional areas of the wires. As a result, routing congestion and a dramatic RC delay (resulting from an increased resistance-capacitance (RC) product) have become important bottlenecks for further interconnect scaling, driving the need for introducing new materials and integration schemes in the BEOL. The current paper studies the damascene process flow that uses a single exposure EUV to create metal lines and 2D patterns at metal half-pitch of 14nm, corresponding to the imec N5 node for logic BEOL layer. A bright field mask with a negative tone resist process was used to develop trenches and transfer these patterns into an oxide dielectric layer. Following this, the trenches were filled with ruthenium (Ru) for electrically testing. Test vehicle included multiple structures, including E-test resistance and capacitance structures, to allow a comprehensive study of the proposed process flow. Metrology requirements and performance at various process steps will be discussed in this paper. Our focus will be on the scatterometry methods that together with machine learning (ML) allow fast and accurate measurements of multiple parameters of interest at large sampling. In the current paper, we present results for inline measurements of line and space critical dimensions (CD), line edge roughness (LER) – after patterning and after hard mask etch, and the prediction of the electrical performance of the metal lines after Ru CMP. In addition, scatterometry ML capabilities for inline tip-to- tip (T2T) measurements are successfully demonstrated.