Presentation + Paper
22 February 2021 Qualification of small alignment mark by on-product overlay performance
Author Affiliations +
Abstract
In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The On Product Overlay (OPO) budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer to wafer (W2W) variations. To save product area and reduce scribe line width, small alignment mark is evaluated to achieve the similar results as reference mark and to optimize the OPO performance. In this work, we will show the experimental results of small alignment mark and investigate the on product overlay performance by simulation.
Conference Presentation
© (2021) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jigang Ma, Frans Bijnen, Edo Hulsebos, Lukasz Macht, Sotirios Tsiachris, Jin Dai, Rob van der Meulen, Miao Yu, Paul Böcker, Jung-Hwan Kim, Hyun Kim, Gwang-Gon Kim, Joon-Seuk Lee, Eung-Ryong Oh, Hong-Bok Yeon, Young-Deuk Kim, Seung-Uk Jeong, Sang-Ho Lee, and Chan-Ha Park "Qualification of small alignment mark by on-product overlay performance", Proc. SPIE 11613, Optical Microlithography XXXIV, 116130J (22 February 2021); https://doi.org/10.1117/12.2584618
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KEYWORDS
Optical alignment

Overlay metrology

Semiconducting wafers

Algorithm development

Device simulation

Process control

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