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12 April 2021 Novel 8-inch wafer scale process for low-cost production of back side illuminated (BSI) imaging sensors
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Abstract
An 8-inch wafer scale process was developed that provides low cost availability of back-side illuminated (BSI) imaging sensors. The process has been optimized to convert standard CMOS and CCD 6-inch or 8-inch wafers from front side illuminated (FSI) sensors to BSI sensors. The process successfully demonstrates wafer planarization, bow correction, bonding to carrier wafers, wafer thinning, re-planarization, anti-reflection coating, through silicon vias (TSVs) and back side metallization. Good wafer thinning control was obtained for a wide range of epi thicknesses varying from 4 microns to 15 microns. The thinner epi is optimized for UV and visible sensing while the thicker epi material is optimized for near-infrared (NIR) sensing. The processed wafers demonstrate backside passivation and anti-reflection (AR) coatings that optimize the QE performance in a variety of bands such as 200nm-300nm, 300nm-400nm and 400nm-900nm.
Conference Presentation
© (2021) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Atul Joshi, David J. Chiaverini, Sachin Kashyap, Vishwanath Madhugiri, Robert Patti, Sangki Hong, and Michael Lesser "Novel 8-inch wafer scale process for low-cost production of back side illuminated (BSI) imaging sensors", Proc. SPIE 11723, Image Sensing Technologies: Materials, Devices, Systems, and Applications VIII, 1172308 (12 April 2021); https://doi.org/10.1117/12.2588181
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