An FPGA-based efficient architecture for accelerating large-scale matrix multiplication

Ahui Huang; Longlong Zhang; Jian Long; Xuan Gao; Yuanxi Peng

doi:10.1117/12.2600185

1 June 2021 An FPGA-based efficient architecture for accelerating large-scale matrix multiplication

Ahui Huang, Longlong Zhang, Jian Long, Xuan Gao, Yuanxi Peng

Proceedings Volume 11848, International Conference on Signal Image Processing and Communication (ICSIPC 2021); 118481Q (2021) https://doi.org/10.1117/12.2600185
Event: International Conference on Signal Image Processing and Communication (ICSIPC 2021), 2021, Chengdu, China

Abstract

In many engineering applications, matrix multiplication is an essential linear algebra operation mode. At present, there are various hardware structures for matrix multiplication. In terms of FPGA-based platform implementation, the systolic array is one of the most important structures. However, due to resource constraints, the existing systolic array has the problem of the small scale of the calculated matrix. This paper first proposes a parallel block algorithm based on systolic arrays, which can efficiently handle large-scale matrix multiplication operations. Then, by optimizing data flow and increasing data reuse, data access overhead is reduced. Finally, we use the matrix multiplication unit to build a complete matrix multiplication acceleration system and deploy it on Xilinx 325T FPGA. Experimental results show that the accelerator achieves a maximum frequency of 125 Mhz through a 25×25 systolic array, which can efficiently process convolution operations in neural networks. Compared with the traditional systolic array, our structure has stronger data processing capabilities. Simultaneously, compared with the linear array and other structures, our structure has the characteristics of low complexity and high efficiency.

Citation Download Citation

Ahui Huang, Longlong Zhang, Jian Long, Xuan Gao, and Yuanxi Peng "An FPGA-based efficient architecture for accelerating large-scale matrix multiplication", Proc. SPIE 11848, International Conference on Signal Image Processing and Communication (ICSIPC 2021), 118481Q (1 June 2021); https://doi.org/10.1117/12.2600185

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