The use of new interconnection technologies to address the interconnect problem encountered in massively parallel computing are discussed. Emphasis is given to a new approach in which the computational units are stacked in the third dimension rather than spread out horizontally on a board. The average interconnect length decreases significantly, resulting in large reduction in system power consumption due to much lower parasitic impedances. Another advantage of shorter interconnects lies in reduced interconnect delays, alleviating problems associated with memory-access/logic-cycle-time discrepancies. This three-dimensional architecture uses wafer-scale integration for each of the planes, eliminating costly and space-consuming packaging at both the chip and board levels.