1 August 1990 High-speed ACR/NEMA interface
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The design and implementation of a standard high speed ACR-NEMA communications interface is described. The upper layers e.g. the Presentation layer, Session layer and part of the Transport/Network layer have been implemented in software. In order to reach the speed requirement of 8M byte/sec. the lower layers e.g. part of the Transport/Network layer and Data Link layer have been implemented in hardware. We have developed and built an interface for an IBM personal computer P5/2 model 50, working under the operating system OS/2. The PS/2, model 50 has been equipped with a fast micro-channel bus, which enables a large throughput. The operating systern OS/2 has a multitasking capability, which enables concurrent programming. In order to minimize the delays, we used this multitasking facility to create a number of parallel operating "threads". The Transport/Network layer functions have been implemented using a receive thread, two send threads and a device driver with three hardware registers. The time to transfer a packet by DMA, to initiate the DMA logic and to execute the required Kernal functions have each been measured and figures are shown. The Data Link layer provides for storage of two packets in two separate random access memories (RAM's). These two RAM's enable a pipelined operation, which minimizes the delay in the Data Link layer.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gerard L. Reijns, Gerard L. Reijns, D. Santilli, D. Santilli, G. Schellingerhout, G. Schellingerhout, A. J. Jochem, A. J. Jochem, Fenno P. Ottes, Fenno P. Ottes, I. W. van Aken, I. W. van Aken, } "High-speed ACR/NEMA interface", Proc. SPIE 1234, Medical Imaging IV: PACS Systems Design and Evaluation, (1 August 1990); doi: 10.1117/12.19005; https://doi.org/10.1117/12.19005


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