This PDF file contains the front matter associated with SPIE Proceedings Volume 12494, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

DRAM cell scaling down to the 14 nm design rule (D/R) has already been productized by major DRAM players such as Samsung, Micron, and SK Hynix. They’re developing n+1 (12~13 nm) and n+2 (11 nm or beyond) so-called D1b (D1β), D1c (D1γ), and D1d (D1δ) or even D0a generation now, which means DRAM cell D/R might be able to further scale down to single digit nm with EUVL adoption for DRAM cell/core patterning. The cell design scaling down is getting slower due to many scaling issues including patterning, leakage, and sensing margin. Major DRAM players have applied EUVL masks (such as SS_BLP/H_SC2) on DRAM and will expand it for the next generation. Current 6F2 cell architecture with 1T+1C will be moving over to 4F2 or 3D DRAM in an 8~9 nm D/R DRAM generation due to scaling limitations, which will be D0b or D0c. Although they change to 3D DRAM with a little relaxed CDs, EUVL will be a must for the performance and yield improvement (defects) in DRAM core areas such as very dense WLD and SA patterns just near the cell array. HKMG DRAM process has been adopted on Graphic DRAM and advanced DDR5 DRAM products by Samsung and Micron, although etching and high-k engineering are different for each. Major NAND manufacturers are still in the race to increase the number of vertical 3D NAND gates, they all have already introduced their own 176L/232L/238L 3D NAND devices. Samsung V-NAND, KIOXIA/WDC BiCS, Intel FG CuA, Micron CTF CuA, SK Hynix 4D PUC, and YMTC Xtacking 3D NAND products are the mainstream for SSD and mobile storage applications. Many innovative processes and designs have been adopted, however, lots of challenges are still there to overcome. Although lithography burdens were reduced by changing 2D to 3D, instead, UHAR etching/cleaning/filling-related developments are ongoing. Micron already exited XPoint memory, and Intel is winding it down as well. For SCM applications, fast NAND and some Emerging Memory (EM) devices such as Z-NAND, XL-FLASH, and STT-MRAM will cover the market needs in the future. Due to the difficulties of the EM materials etching, they’re currently limited to embedded and low-density applications only. We’ll discuss current and future challenges on DRAM, 3D NAND, and Emerging memory including process, design, and materials.

In applying EUV lithography to fine-pitch random logic ICs, systematic defects and EPEs take on stochastic nature, and stochastic hot spot predictions are desired. This is challenging, however, since those defects generate probabilistic because of strong correlations. This paper analyzes and predicts stochastic hot spots in arbitrary patterns. We describe the formation of patterns and their anomalies as the probability of molecular sub-cluster generation, based on the 1st principle Monte Carlo simulation and the discrete dev/etch model. The sub-cluster generation well describes correlated pattern/anomaly formation. Correlation is squeezed in the direction normal to pattern edges and spreads as the image slope is relaxed. It is independent of pattern size but dependent on materials, and thus its impact increases with shrinking pattern sizes. Pattern polarity changing probability rises unexpectedly when the reaction in a shallow image slope area enters a certain reaction density range. This is because the inter-molecular correlation range approaches optical image size, and it can be the origin of stochastic hot spots. A deep neural network effectively predicts this phenomenon and infers the probabilities of stochastic EPEs and hot spots.

EUV lithography has been one of the key factors that enables the continuation of semiconductor scaling beyond N7. While it is a vital technique for the HVM of the most recent advanced logic and DRAM devices, the EUVL still needs more efforts in order to fully exploit its capability and extend the application. One particular aspect that has been considered as of critical importance is the optical/chemical stochastic effects which may cause L/S, contact pattern defects limiting the efficiency of EUVL. The simplest way to alleviate the stochastic effects is to employ the higher EUV exposure dose; however, this approach is impractical as it obviously leads to even lower productivity. In this work, the alternative chemicals - such as EUV PTD developer and NTD rinse which are specifically prepared to overcome the stochastic effects - are examined to enhance the performance efficiency of EUVL. The focused features that thoroughly explored are EUV dose, local CD uniformity, PR swelling, pattern collapse, and defects. It is found that, with the chemical composition modification of developer and rinse, EUV pattern fidelity can be effectively optimized resulting in extended process window and improved productivity. It is expected that this work would not only facilitate the extension of EUV application but also help understand how EUV resists behave when they are under the influence of ancillaries.

To print ever smaller features at high contrast projection lithography technology has evolved to shorter wavelength light and larger NA. After enabling the EUV wavelength, the industry is looking into increasing the NA. This study aims to identify EUV specific challenges regarding NA scaling beyond 0.55. We study if EUV imaging can still work at this higher NA and whether specific changes to the mask stack are required. At NA's much higher than 0.55, new effects like polarization will play a role, and larger impact of ultimate mask resolution and material interactions is expected. Already at NA 0.55, a small contrast loss is predicted due to the use of unpolarized light in the scanner. Further increasing the NA will enhance the contrast loss. We study these polarization effects in detail and assess their impact quantitatively for a set of generic building blocks. In addition, the larger incidence angles on mask when the NA increases above 0.55, will further enhance the M3D effects forcing additional mask changes. To enable proper imaging at high incidence angles, new mask architectures, that include changes in the EUV mask absorber and multilayer, will have to be tested using rigorous simulations.

ASML NXE (0.33 NA) scanners are now commonly used for High Volume Manufacturing (HVM) of 7nm and 5 nm logic devices as well as 1z memory node devices. In 2021, ASML has introduced the NXE:3600D scanner to the market, targeting 3nm logic and 1a and 1b memory nodes. This system has entered the HVM phase and is shipping in volume. In this paper we will share the latest performance, with excellent imaging, overlay and productivity results. For the latter we will show record performance of 185 Wafers per Hour at dose 30mJ/cm2 and over 3000 Wafers per Day at customer. Furthermore, we will address the ASML roadmap and introduce the NXE:3800E scanner. The NXE:3800E will first ship in the fourth quarter of 2023, targeting the 2 nm logic node. Lastly, ASML will show its carbon footprint and energy reduction roadmap.

The interaction of EUV light with matter is a critical step in EUV lithographic processes and optimization of the optical material parameters of photoresists and reflector/absorber stacks is crucial to harness the full power of EUV lithography. To optimize these materials, accurate measurements of EUV absorption and reflection are needed to extract the corresponding actinic optical properties and structural parameters. Here, we report on two endstations within imec’s AttoLab that enable actinic EUV absorption and reflection measurements. We commission these tools with measurements on model thin film and photoresist systems and provide extracted optical parameters as well as absorption kinetics, respectively. These results showcase the power of these tools for providing crucial data for material optimization and lithographic simulation.

We study the effect of phase variability as an aspect of mask roughness that could contribute to Edge Placement Error (EPE) on the wafer. Phase variability in the diffracted light arises through non-specular reflection from rough surfaces or local thickness variation of the ruthenium capping layer. This leads to a speckle pattern in the aerial image intensity. Simulations were performed using representative values of mask rms and correlation length from literature and rough absorber contours extracted from mask images. The aim was to identify how such a contribution manifests in the lithographic performance of a 44 nm pitch L/S pattern. In simulation, this type of mask roughness leads to increased CD and pattern placement variability in defocus, local best focus shifts and Bossung tilts. Measurements with AIMS EUV of the pattern on reticle showed similar effects in the aerial image. Finally, we gauge the impact on-wafer by isolating the systematic variability through focus for two illuminations, one sensitive to speckle and another insensitive one.

Precise knowledge of the wavelength-dependent refractive index of materials is required to accurately design, build and calibrate the in-band and out-of-band performance of EUV/x-ray instruments. Such instruments include exposure and patterning tools, imagers, microscopes and spectrometers for photolithography, plasma physics, synchrotron and laser science, solar physics and astrophysics. Yet, the available refractive index values in the EUV/x-ray are often unreliable. This is due to the extreme sensitivity of materials to contamination and oxidation, to the difficulty in fabricating appropriate thin film samples, to the presence of near-edge absorption fine structure, and to multiple reflections present at the longer EUV wavelengths, which are complicating the measurements. We are presenting a new methodology to measure the EUV refractive index and new sets of measurements for several important EUV materials. We use combinations of transmittance and reflectance data in the spectral range 826.5 eV (1.5 nm) to 15 eV (82.5 nm) and reveal for the first time highly resolved fine structure in the regions of L, M, N and O absorption edges, in both the absorptive and dispersive portions of the refractive index, resulting in improvements of up to a factor of 3 compared to earlier values. The improved refractive index accuracy is validated by sum rule tests and by simulating experimental data of multilayer coatings containing these materials.

The first planned Digital Scanner product, DS248, will have the optical resolution of 110 nm and overlay accuracy of less than 10 nm, the same level as a KrF mask scanner. In addition, DS248 has more application areas, such as individual chip customization and large-area printing up to wafer size, with KrF resolution, which are not possible with the current mask scanner but will be beneficial for performance enhancement of semiconductor devices in future. The latest exposure results of DS-POC, which has the similar imaging performance with DS248, are introduced including chip ID exposure on entire 200 mm wafer and exposure of wafer scale integration substrate. Simulation data of high aspect ratio patterning with high resolution by means of integration of multiple heads of solid-state laser is described. Development progress of DS’s pixel mask conversion software that directly generates pixel mask from target pattern with OPC is reported.

With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.

Despite being crucial in an optical lithography process, “dose” has remained a relative concept in the computational lithography regime. It usually takes the form of a percentage deviation from a pre-identified “nominal condition” under the same illumination shape. Dose comparison between different illumination shapes has never been rigorously defined and modeled in numerical simulation to date. On the other hand, the exposure-limited nature of EUV lithography throughput demands the * illumination shape being optimized with the physical dose impact consciously taken into consideration. When the projection pupil is significantly obscured (as in the ASML EXE high NA scanner series), the lack of a proper physical dose constraint may lead to suboptimal energy utilization during exposure. In this paper, we demonstrate a method to accurately model the physical dose in an optical lithography process. The resultant dose concept remains meaningful in the context of a changing illumination pupil, which enables co-optimization of imaging quality and a throughput metric during the Source-Mask Optimization (SMO) phase, known as the Dose-Aware SMO. With a few realistic test cases we demonstrate the capability of Dose-Aware SMO in terms of improving EUV throughput via reducing the effective exposure time, in both regular and obscured projection systems. The physical dose modeling capability in computational lithography not only addresses those immediate challenges emergent from EUV throughput, but also opens the gate towards a broad class of exciting topics that are built upon physical dose, such as optical stochastic phenomena and so on.

EUV lithography has been adopted worldwide for High-Volume Manufacturing (HVM) of sub-10nm node semiconductors. To support HVM, EUV pellicles were introduced by ASML in 2016. More recently, several novel pellicle materials have been developed to offer higher transmission and support higher source powers. The current focus is on two classes of pellicles to support the upcoming NXE:3800 and the associated N2 node, and beyond: Si-based composites and CNT-based pellicles. In this paper, we will give an overview of scanner integration results of current EUV pellicles, both Si-based composites and CNT-based pellicles. This overview will cover high-level aspects of transmission, imaging, robustness and lifetime; as well as underlying contributors such as EUV-uniformity, EUV-reflectivity, flare and DUV-reflectivity. Reviewing achieved performance will illustrate the suitability of these materials to support advanced nodes in production. Additionally, the anticipated future performance of EUV pellicles when used with increasing EUV source powers and high-NA scanners will be provided.

EUV lithography has been implemented in high volume wafer production. Consequently, maximizing yield is of major importance. One key component to achieve optimal yield is using a pellicle to hold particles out of the focal plane and thereby minimize the printing of defects. The carbon nanotube (CNT) pellicle is a membrane consisting of a network of carbon nanotubes, which demonstrates EUV transmission up to 98%. The challenge is to balance the CNT material parameters for optimal performance in the EUV scanner: low probability for particles to pass, high durability in the scanner environment, while maintaining high transmission and low impact on imaging. While our earlier reporting on full-field CNT pellicle exposures demonstrated minimal impact on imaging, the focus of the current paper is on extended exposures on NXE:3400. In the scanner, the EUV light induces a hydrogen plasma that etches the CNTs, resulting in decreasing membrane density and increasing EUV transmission. In this work, we quantify the CNT pellicle etch rate in a real scanner environment and correlate the findings to those obtained in an offline test setup. Our exposures were performed using two different pellicles, with EUV transmission of 89% and 95%, for up to 3000 wafers. Additionally, we demonstrated the effectiveness of pellicle purification prior to mounting on the reticle, which is important to avoid contamination from the as-fabricated CNT pellicle onto the reticle surface. Current ongoing developments focus on further increasing the pellicle durability in the scanner environment. The presented results demonstrate the potential of a CNT-based pellicle at high EUV powers.

This study investigates the role of EUV mask absorber materials defects on stochastic defect formation in a lithographic process using simulations. The purpose of these simulations is to compare absorber materials by their role of affecting stochastic defects as well as CD performance in the lithographic process. The absorber materials are tested for bright and dark field masks using low defectivity and CD criteria to define process windows for different pattern types. The process windows are examined to identify and compare an estimated process window overlap that takes patterns, material, CD performance and defectivity into account. The defectivity of the stochastic process simulation was increased using a modification to the distribution of chemical components that resembles the effect of PAG and Quencher molecules forming clusters. The study demonstrates that the overlap of low defectivity process windows strongly depends on the types of patterns and the absorber material.

The extreme ultraviolet (EUV) pellicle on the EUV mask is used to prevent the image distortion, and the lifetime of the pellicle is important because it is directly related to the yield. However, particle defects can significantly impact the lifetime of the pellicle, causing thermal or mechanical damage such as deformation or increased temperature. To study these effects, we explored how particle defects affect the pellicle, including scenarios where defects on the pellicle or collide with it. We found that there was no temperature and stress accumulation with repeated exposure of the pellicle regardless of the defect exitance. The collision of flying particles gave little mechanical effect with the known impulse inside the scanner. The metal-silicide core pellicles showed better thermal stability compared to the poly-silicon core pellicles and that could be the reason why metal-silicide pellicles showed longer lifetime.

Layout designs are reaching the resolution limit for 0.33NA extreme ultraviolet lithography (EUVL) systems, with 0.55NA high-NA on the horizon. Alternative mask designs at reduced absorber thickness for higher image contrast have become necessary. Novel absorber candidates are classified as attenuated phase shifting mask (attPSM) absorbers, high-k mask absorbers and index matched absorbers (n ≈ 1) based on the complex refractive index (n – ik). We identify absorber candidates through effective media approximation (EMA) model and discuss design considerations for attPSM absorbers. Optimum phase shift for EUV attPSM is higher than π and it is influenced by the absorber material, diffraction angle at the mask, mask pattern, NA and absorber reflectivity. Index matched mask absorber designs with higher extinction coefficient are also proposed as promising candidates.

Transistor pitch scaling drives the evolution of chip design. The late arrival of EUV lithography prompted the adoption of multiple patterning using 193i to continue transistor scaling. To facilitate multiple patterning integration schemes, the 2D design style was abandoned and unidirectional design style became dominant. As transistor scaling continues further, the demand on routing resources can exceed their supply leading to routing congestion. Exploration on 1.5D or curvilinear routing to resolve higher Metal 2 usage was studied. Nowadays, EUV lithography re-introduced single patterning for the most advanced nodes. At the same time, Multi Beam Mask Writer (MBMW) enables true curvilinear masks. The use of curvilinear routing can potentially resolve routing congestion and more relax design rule check by combining EUV lithography and MBMW. This paper focuses on the challenges in optical proximity correction (OPC) on a design with curvilinear routing. Wafer data will be evaluated to assess quality. The target design is a D-flipflop using 2D and curvilinear features in a local interconnect layer to reduce the congestion. The base pitch of this design was scaled from 40nm to 32nm. The test design was then OPCed using Model Based OPC and Inverse Lithography Technique. Finally wafer data and process window analysis across the pitch range from different OPC variations will be revealed.

To maintain good critical dimension control, optical proximity correction (OPC) has relied on fast compact models to capture the underlying lithography process in advanced nodes. Compact models have always been deterministic in the sense that they predict the average dimensions or contours on wafer. With the introduction of extreme ultraviolet (EUV) lithography, this approach breaks down due to large variabilities in EUV lithography processes. Recently, empirical correlations were found between this variability and imaging metrics, allowing the development of compact models. Such stochastic models have been used successfully to predict hotspots. In this paper an attempt is made to apply such stochastic models during OPC to reduce the number of stochastic failures. Different OPC strategies are applied on an advanced random logic and SRAM design, focusing on a via layer with a calibrated stochastic model. Through simulations, we show that the failure rate can be reduced by using a stochastic model during OPC, at the expense of edge placement error. However, when reducing the stochastic band width to match the process variation band width, no meaningful differences were observed between process-window OPC and stochastic OPC due to uniformity of pattern dimensions in sample layout.

In this paper, we present a new approach to EUV source optimization which automatically generates a binary solution for the intensities of almost all the pixels. The benefit of such a binary solution is that the source power is distributed evenly over all the illuminated pixels, thus avoiding large intensity spikes which can lead to accelerated, radiation-induced degradation of certain parts of the imaging system.

Tail CD was previously introduced as an empirical metric that correlates the CD distributions rather than mean CD to observed defect failure rates. It was found useful for the prediction of defect process windows, but also showed its limitation on the “merge” defect in dense hexagonal contact hole patterns. Results of a follow-up study are shown here to address this limitation by exercising the Tail CD concept on a new metric called ‘Wall CD’. The Wall CD showed orientation-depended performance that could be traced back to the illumination shape explaining the predominance of diagonal merges in the contact hole failure rates. Verification of the new approach demonstrated a significant improvement in the accuracy of the predicted defect process window. Furthermore, we utilized data analytics techniques to investigate the impact of additional parameters collected during the Wall CD extraction. This analysis demonstrated, in addition to the mean and variance, the importance of the higher statistical moments (skew, kurtosis) of the distributions for the prediction of defects and the relevance of incorporating further parameters into defect models.

By adopting the new design of the optics within the scanner, high-NA (0.55NA) EUV lithography enables higher resolution, which will push the EUV single patterning down to pitch 16nm (k1=0.34, the same k1 value as pitch 28nm for 0.33NA EUV single patterning). Therefore, 0.55NA EUVL is projected to print the most critical features of 2nm node (and beyond) logic chips with less patterning steps than 0.33NA EUVL, and is highly expected by the industry. Besides, novel low-n low-k absorber attenuated phase shift masks (low-n attPSMs) are commercially available recently, which have shown substantial imaging, as well as patterning performance improvements both in simulations and experiments. Thus, in this paper, we evaluate the feasibility and limits of logic metal scaling with 0.55NA EUV single pattering using source mask optimization tool, both binary and low-n attPSMs are used to pattern an imec N3 (pitch 28nm, foundry N2 equivalent) random logic metal design and the linear scaled versions (down to pitch 18nm). The impact of design orientations (horizontal vs. vertical) and mask tones (dark field vs. bright field) on patterning fidelity and overall process window is evaluated.

Control of the Local Critical Dimension Uniformity (LCDU) and the associated Edge Placement Error of contact holes (CHs) is important for the implementation of EUV lithography in high-volume production today and for future nodes. The Systematic part of the LCDU is governed by the local CD variation on the mask, multiplied with a Mask Error Enhancement Factor (MEEF). Recent studies have shown that the relevant MEEF to predict the LCDU systematics is the Local MEEF, where not all CHs grow at the same time. This stands in contrast to the more commonly used Global MEEF, that quantifies the wafer CD impact of all CHs growing simultaneously on mask. In this work, we experimentally study how the systematic LCDU, and the Local and Global MEEF depend on illumination condition and mask variability strengths and signatures. We expose a test mask with programmed local CD variability on an NXE:3400 exposure tool and perform anchored CDSEM metrology on the mask and on wafer. Our results show that the illumination condition and the local mask CD fingerprint impact the Global and Local MEEF independently in a non-trivial way. Two pupils with similar Global MEEF show a 55% difference in Local MEEF and systematic LCDU component. Optimizing the pupil for Global MEEF therefore does not guarantee an optimum Local MEEF (or Systematic LCDU).

In this paper, the role of sub-resolution assist features (SRAFs) in 0.55NA EUV lithography is discussed. We demonstrate how SRAFs help with pattern placement error (PPE) control through exposure focus on horizontal line/space structures using dark field masks. Even for 26nm minimum pitch design rules (relatively high k1), SRAFs help control the focus budget. Next, an analysis of the mask variability budget is done. We establish that a tight CD and placement control on the SRAFs is required for keeping PPE through focus under control. A variability budget of 0.5nm (1X) for both CD and PPE is shown to be just sufficient for maintaining a 40nm depth of focus (DoF) in the absence of process variability. PPE variability due to resist stochastics further reduces the available DoF.

Next generation EUV scanners have been introduced with anamorphic, obscured multi-layer optics for operation at 0.55NA. Aberrations are of particular concern with high-NA EUVL, as the 13.5nm wavelength has returned wavefront phase errors to near I-line levels. With the central obscuration necessary so that additional lenses aren’t needed, the Zernike basis is no longer orthonormal, resulting in coefficient values which are dependent on the number of fitted terms. For an industry transition to a Fringe Tatian wavefront description to be successful, it is important to incorporate and carryover the intuitive understanding of the imaging effects of common aberrations. Using modifications to Prolith and Dr.LiTHO lithography simulators, this work defines a simulated lithography lens using the Fringe Tatian basis and includes simulations of common patterning conditions for next generation high-NA EUV nodes.

An increased interest to stitching for High NA EUVL is observed; this is driven by expected higher demand of larger size chips for various applications. In the past a recommendation was published [1] to have 1-5 um band where no critical structures of a High NA layer would be allowed. In [2], we have introduced new insights on at-resolution stitching. In this publication, we present new experimental results obtained on NXE:3400B scanner. In the past we showed NXE feasibility results of vertical lines and contact holes stitching at relaxed resolution (40-48 nm pitch) in a single wafer location. In this study we evaluate stitching behavior through slit at more aggressive resolutions (P36 and P24 lines / spaces). We provide an overview of interactions in the stitching area such as aerial image interactions, absorber reflection, absorber to black border transition, black border vicinity impact and show corresponding experimental and simulations results. We formulate initial requirements for black border edge placement control and show performance of new masks. For stitching with low-n masks, we discuss using sub-resolution gratings to suppress the elevated mask reflectivity. We show rigorous simulations of stitched images, its sensitivity to overlay errors and propose mitigation mechanisms for OPC. Finally, an overview of stitching enablers will be described: from improved reticle black border position accuracy and absorber reflectivity control to mask resolution and OPC requirements.

The foundations of leading edge DRAM manufacturing are built on accurate EUV lithography exposures in close synergy with cutting-edge immersion layers as well as advanced patterning schemes (e.g. self-aligned multiple patterning). Final device yield critically depends on the subsequent and accurate stacking of multiple layers with device features of precise width and edge placement. To support the ever-decreasing requirements for both the EUV as well as the DUV, (edge) placement accuracy, scanner enhancements are required on both platforms. In this paper we report on the improvements of the NXT:2100i immersion scanner to further reduce the (edge) placement errors within the die (intra-field) and across the full wafer (inter-field). The NXT:2100i incorporates a new projection optics with built-in distortion manipulator that extends the intra-field correction capability for both X and Y directions. The external overlay interface is extended with the distortion manipulator degrees of freedom to handle high spatial frequent distortion data of a to-be-matched scanner or high spatial frequent overlay fingerprints measured by after develop or after etch metrology. Thermal conditioning of the reticle is improved with a fast conditioned internal reticle library resulting in lower reticle-to-reticle temperature variation. Improved lens metrology (aberrations) and reticle align accuracy (alignment/overlay) is achieved with a better integrated image sensor. Improved alignment accuracy and reduced alignment process dependencies for wafer alignment are realized with 12-colors parallel measurements and by adding more alignment marks measurements at the wafer measure side without throughput impact. In concert with the hardware components, various software algorithms are updated, yielding improved inter- and intra-field overlay setup and improved reticle heating induced overlay. We will detail the specific module performance items as well as the system performance of the NXT:2100i scanner, both in reference (DRAM relevant overlay) to DUV as well as to EUV scanners.

In an earlier publication, we evaluated simulation methods to explore overlay performance implications when a highNumerical Aperture (high-NA) Extreme Ultra Violet (EUV) exposure is mixed and matched with a 0.33NA EUV full field exposure. The present contribution goes beyond the method description and aims to quantify the overlay performance impact in such a mix and match case, giving insight into the influence of different sets of overlay corrections. To this aim, the Mont Carlo engine has been updated to accommodate overlay corrections with up to 57 parameters. Since high-NA EUV is not yet available, typical overlay correction terms from IBM’s 0.33NA EUV tool have been used to approximate a realistic image placement error fingerprint for our simulations. As a result, we demonstrate the benefit of various overlay correction sets, and the detrimental effect when using different masks for top and bottom half fields. Such information can also help to infer design layout placement decisions to avoid hot spot regions.

Strong challenge on EUV photoresist includes overcoming the stochastic effect caused by the lack of photons. At the different dose range, the relationship of LCDU and dose moves differently. This ‘breaking point’ in the relationship of LCDU and dose is measured at different pitches with photoresists and masks with different uniformity. Smaller pitch patterning requires more dose, whereas photoresist and mask does not affect the ‘breaking point.’ Combining these speculations show the limitation of the EUV at the low dose process, which is critical for high volume manufacturing.

Aggressive off-axis illumination must be used to resolve line space pitches of 28nm and below. The consequence is that the best focus (BF) shifts a lot and depth of focus shrinks rapidly through pitch. This is mainly due to the mask 3D effects. To reduce the impact the best-known method is to introduce sub-resolution assist features (SRAF). We explored wafer printing with SARF size of 6-8 nm and analyzed BF and DOF impact. Clear SRAF sizes of 6-8 nm do not print with PCAR but some 7-8 nm clear SRAF printed with NTD MOR due to the higher resolution and over exposure preference. Then we validated the experiments with SLITHO simulation tool, and we found a good experiment-simulation match of BF/DOF/EL/MEF w and w/o SRAF through pitch with the three P28 illumination candidates. Overall SRAF can improve the DOF and exposure latitude (EL) for the given pitches with SRAF capable and help shift the BF to the favored focus direction. With the validated model we further study BF/DOF/EL/MEF w and w/o SRAF through pitch with the small/medium/large sigma illuminations designed for 28nm pitch, with traditional TaBN and other three candidate absorbers. We will also discuss the SRAF size and placement sensitivities. Through this work we are confident to implement SRAF to enlarge the common process window for a large range of pitches.

Metal oxide resists (MORs) have been becoming one of the most promising candidates that facilitates the extension of EUV single exposure by improving both lithographic resolution and etch selectivity. However, to succeed high volume manufacturing, the MORs process should be robust and persistent regardless of lithographic process fluctuation that might occur. In this work, the systematic examinations on the MORs process have been explored in order to understand the MORs patterning mechanism. We found that the ADI CD (After Development Inspection Critical Dimension) could be varied with trivial fluctuation of EUV radiation, humidity, and incomplete condensation reaction. In particular, the humidity around a coated resist was the important element that affected the condensation reaction and determined the insolubility of MORs against developer solution, which consequently defines the ADI CD. Thus, the methods that enable not only the moisture control but the sufficient condensation reaction were carefully examined. Moreover, it is investigated whether MORs can enhance further the etch selectivity while reducing the intrinsic resist defect. Several strategies have been implemented, which allow the CD variation to be reduced and the process window to be enlarged compared to the early stage MORs processes.

The lithography industry has historically striven to improve resolution by reducing wavelength and increasing the lens’ numerical aperture (NA). The introduction of 0.33 NA extreme ultraviolet (EUV) lithography into high-volume manufacturing (HVM) represents the largest jump in resolution ever achieved by the industry. However, even this resolution is not sufficient for the patterns required for beyond the 2 nm logic technology node. This is due to low contrast and the diffraction limit of current EUVL scanners for the mask patterns required for these nodes. Instead, the resolution must be improved by increasing the NA. This will also increase the contrast of patterns which had insufficient contrast at 0.33 NA, which will in turn improve LCDU and defectivity. This change is not without its challenges though. Increasing the NA from 0.33 to 0.55 will cause a significant reduction in depth of focus. In addition, stronger mask 3D effects can cause pattern dependent shifts in best focus. As a result, the common overlapping process window of several critical patterns can become strongly diminished. The use of anamorphic optics will require two separate half-field exposures to obtain the equivalent of a single full-field exposure on current EUV and DUV scanners. For some chip sizes, this will require stitching two half-fields together to pattern the full chip area. In previous technology nodes, the process window could be improved using SMO and SRAFs. In addition, over the last five years, the industry has put significant effort into studying alternative absorbing materials. These materials can significantly reduce the mask 3D effects by reducing the thickness of the absorber. The use of alternative absorbers alone will not be sufficient for improving the overlapping process window. Instead, several techniques must be simultaneously utilized in order to ensure sufficient overall process window. Optimization of overlapping process windows is critical for successful insertion of high-NA EUVL into HVM. In this paper we analyze how the process window of critical patterns can be optimized by using different optimizations. We will show for realistic mask designs how process window can be improved in different process steps. Double exposure from half-field stitching will also be included in the process evaluation. We use both rigorous and compact modeling in a complimentary fashion for overall process optimization analysis. All techniques presented in this paper accurately model the anamorphic, centrally obscured optics of the upcoming next-generation high-NA scanners.

Imec logic N2+ design rule defines a minimum via pitch of 36nm. An EUV single patterning solution at 0.33 NA is explored on a random logic via design. From an earlier simulation study , it was shown that Ta-based bright field mask delivers the best resolution enhancement technology (RET) solution. In this paper the simulation results will be validated on wafer. Negative-tone development (NTD) with a metal-oxide resist process using a bright field (BF) mask and positivetone development (PTD) with a chemically amplified resist process using a dark field (DF) mask are compared. In addition, source-mask optimizations (SMO) including sub-resolution assist features (SRAF) were used as a RET, and optical proximity correction (OPC) was carried out on the design clips to achieve optimum lithography performance. We report the best choice among the listed options, and present our recommendation on OPC, RET and process based on the simulation and wafer data in order to improve the resolution, therefore extending the single exposure pitch limit.

This paper presents a study on a new method to create exposure profiles that are optimized for selected die areas where patterning is critical. This new “region of interest leveling (L-ROI)” method caters for trends in the memory market, where intra-die topography with height steps between for instance cell and periphery areas is commonly observed for several 3D-NAND and DRAM device layers. The method takes advantage of the presence of (periphery) die areas where for some device layers patterning is less important than for other, more critical die areas, like the cell area in 3D-NAND. The L-ROI exposure profiles are insensitive to intra-die topography and to variation of the intra-die topography. They result in tighter focus uniformity (FU) in regions of interest, and thus in tighter CDU as well, than conventional exposures at the cost of an accepted performance degradation in other, non-care areas. Results of a study on a VNAND channel hole layer are presented, including focus performance simulation results and CDU measurement results from in-resist verification of L-ROI functionality on an immersion lithography scanner. The latter show a 31.7% CDU improvement with respect to conventional exposure mode.

ASML NXE scanners are installed at customer factories and being used in high volume manufacturing (HVM) of leading semiconductor devices. EUV sources have improved performance and availability. In this paper we provide an overview of 13.5nm tin laserproduced-plasma (LPP) extreme-ultraviolet (EUV) sources enabling HVM for the most advanced nodes. Sources at customers operate at ~250 Watt power with high availability. Progress in Collector Lifetime and EUV Source performance is shown. High NA EUVL Scanners are in development for future nodes of device manufacturing, with new requirements for source geometry and few new requirements for source performance. In this paper we additionally discuss our progress on the High NA source towards shipment to the customer later this year. Finally, we provide an update on power scaling at ASMLs research systems including reaching a new 600W milestone for EUV Sources and the next steps towards even higher powers.

High numerical-aperture (NA) extreme ultraviolet lithography (EUVL) system has been highly desired [1-3] and is now under construction at imec-ASML high-NA laboratory in Veldhoven. However, there are still many challenges to realize high-volume manufacturing (HVM) by high-NA EUVL; Line edge roughness (LER) mitigation is one of the key elements. In our previous research, we studied how normalized image log slope (NILS) and resist film thickness (FT) affect resist LER by exposure at NA 0.33 on NXE:3400 and S-Litho EUV [4] . However, mask absorber/tone, exposure dose and postexposure bake (PEB) temperature were not focused on for decreasing LER. They have the potential to mitigate resist roughness as illumination and resist thickness also have. Unbiased LER (uLER) values of metal oxide resists (MOR) were experimentally measured on half pitch 14 nm line and space (L/S) under several mask absorber/tonality, dose and PEB temperature. Per mask absorber/tone the NILS was varied by using different illumination shapes. Low-n masks exhibited higher NILS for the same illumination shape, which resulted in lower resist LER on wafer. It was also found that mask tone can contribute to LER mitigation. According to detailed investigations about mask roughness, mask error enhancement factor (MEEF) and flare by CD-SEM measurements and S-Litho EUV, the most likely reason for LER difference is flare increase given by mask tone change. From dose and PEB temperature variation study, dose was apparently more dominant to resist roughness than PEB temperature.

We report the development progress of key technologies for the Sn-LPP (Laser-produced-plasma) EUV light source system at Gigaphoton Inc. EUV light source systems have come to be used for a wide range of applications such as lithography exposure tools and inspection tools. In both applications, high power and high radiance together with high operation availability are required. To meet these requirements, we developed and optimized a long lifetime droplet generator, a pre-pulse irradiation scheme, laser-droplet shooting control and debris mitigation with hydrogen gas for lifetime extension of the EUV collector mirror. To achieve high operation availability, the collector mirror and the Sn droplet generator lifetime are the most important contributions. The collector mirror lifetime is mainly determined by the reflectivity degradation due to sputtering, implantation, and deposition by Sn ions, Sn atoms, Sn fragments, and hydrogen-induced blisters. The developed droplet generator with in-line Sn fuel feed system has demonstrated stable droplet generation for more than 1,300 hours in our EUV light source. An advanced pre-pulse technology achieved higher CE without increasing the energy of the Sn plasma. Our Sn mitigation scheme works efficiently for lower energy ions and lower fragment deposition rates. Our optimized in-situ shooting control system improved the EUV energy and dose error. With these technologies, we have demonstrated no reflectivity degradation (i.e. no fragment deposition) on EUV sample mirrors after 25 Billion pulse irradiation tests. The advanced capping layer has demonstrated to suppress blister formation.

To get better and more stable performance in the mix-and-match of scanners in the fab, the matching of the illumination between those scanners is a must-have for HVM ecosystems. “Traditional” methods have been developed throughout the past years to characterize and correct for any dematching of illumination between tools. In the case of a fast growing fab the latter is not viable anymore because the flow is not automated, and the measurement acquisition methods are not robust enough to mitigate long and fastidious manual intervention of the engineers. In the paper, after reminding the legacy method, we will explore the way of using contour-extracting software to improve quality, runtime, and automation of the full analysis flow. The work will be divided in three parts: - Improve data collection quality and get robust measurements - Set an automated flow based on a contour-extraction software for post-treatment of SEM images and contour analysis - Automatize all the flow to decrease the time between test wafer exposure and validation of the matching

As increasing complexity of1 devices and scaling have continued to push the lithography to low k1 limit, lithographic scientists have been developing various resolution enhancement techniques (RET) to extend 193nm immersion lithography. Chrome-less phase shift mask (PSM) is one of the RET techniques which can produce frequency doubling to half the pitch. The shifter is changed from MoSi to quartz for chrome-less PSM. And the shifter in quartz that is challenging to control at mask etch process. This will cause phase error, lead to image shift and CD asymmetry impacts wafer CD uniformity (CDU) due to intensity imbalance. In this paper, based on aerial image simulations, the conditions to generate frequency doubling have been studied, the resolution limit of the frequency doubling has been investigated. The phase error tolerance of frequency doubling for accepted wafer CDU referring ITRS road map plus budget breakdown to reticle CDU contribution has been studied. The phase error tolerance for smaller pitch is predicted with polynomial fitting extend too.

193i SAQP has allowed industry for continued BEOL metal pitch scaling, but as metal pitches become even tighter EUV SADP becomes an interesting alternative. In this context we have explored within our dual damascene 3ML test vehicles how the EUV SADP process compares to 193i SAQP for printing MP21 M2 lines. Our first EUV SADP results already show a better wafer CDU compared to our POR 193i SAQP process.

In advanced technology nodes, the focus window becomes tighter to achieve smaller CD features while maintaining or improving product yields. During the past decades, focus spot monitoring (FSM) has been a critical topic in high-volume manufacturing, not only for minimizing the contamination impact on focus performance but also for scanner productivity concerns if wafer table cleaning needs to be executed. Although there is a dedicated FSM option combined with automatic wafer table cleaning from the exposure tools, the users often need to be careful to design the threshold and monitor the area by different products and layers, to prevent false positive alarmsthat impact the productivity of scanners. In some cases, a small focus spot threshold can cause more false positive alarms at the wafer edge area due to the edge roll-off effect on the wafer table and steep wafer topography, which brings difficulty to detecting small focus spots due to contamination. In our study, we compare the classic FSM provided by exposure tools to a newly developed automated FSM mechanism. There are several mathematical steps and approaches implemented into our new type of FSM to reduce false positive focus spot alarms. For comparison, we evaluated the performance of classic and new FSM methods on different layers, which showed special topography, edge roll-off effect, or strong intra-field signature. Finally, a new robust and user-friendly FSM method has been demonstrated and proven that even with a tight threshold, the false positive alarm especially around the wafer edge area can be fully eliminated.

Integrated Circuit (IC) fabrication requires performing a long sequence of complex process steps. Among them, photolithography patterning plays the most important role to define the dimensions, doping regions, and intercon nections for each device. With the advancement of lithographic processing, minimum feature sizes continue to shrink, and the devices become denser. At the same time, the specifications for overlay accuracy, wafer critical dimension uniformity, and acceptable focus deviations also become tighter. Hence, even nanometer-sized defects on wafer substrates can ha ve a crucial impact on the quality of the lithographic exposures and limit the performance of such devices. Detection and elimination of such surface defects (“focus spots”) at the early stage of processing have been of primary concern to prevent the loss in manufacturing productivity and significant product yield degradation. In this paper, we present a focus spot monitoring framework to detect focus spots and chuck spots accurately by using wafer leveling data. We discuss different strategies how to detect focus spots, how to classify them, and how to monitor and correct them effectively. We evaluate existing focus spot monitoring solutions and how to improve upon them. Altogether, a stable, reliable focus spot monitoring solution is described for optimal focus corrections and rework decisions.

The requirement of larger common overlap process window in EUV patterning is getting stronger when the design pitch continues to shrink. The reflective optics in EUV generate various imaging issues due to mask 3-dimensional (M3D) effects. Therefore, sub-resolution assistant features (SRAFs) insertion is preferred for the resolution enhancement technology. SRAFs insertion can create a dense optical environment that will prevent strong best focus shift between semi-isolated and isolated features. From the previous study, SRAFs insertion and stochastic printing can be modeled and verified with a flow utilizing a compact resist 3D model (R3D) in conjunction with stochastic model. In this work, additional SRAFs investigations and studies extend to a better choice of alternative EUV mask absorbers that can mitigate M3D effects and have better lithography performance. In this paper, a low-n dark field EUV mask with regular hole grid design and positive tone development (PTD) is considered. The SEM (scanning electron microscope) images of through pitches with various SRAFs sizes and combination of SRAF to main space are collected. The SRAFs printing pixels can be captured and modeled with compact resist stochastic modeling. The results can be verified using average printed area (APA) metric with a R3D model and the simulation studies have proved the SRAFs printing sensitivity to the photomask biases.

Fast ion debris generated in laser-tin droplet interaction is known to degrade the reflectivity of the EUV collector mirror, posing a challenge to the commercial use of the EUV source. In the present work, we conduct one-dimensional fully kinetic Particle-In-Cell simulations using PSC code that is capable of capturing fast ion debris formation. We discuss the progress in the implementation of physics modules for the PSC code that is required to replicate the EUV generation process in detail. We demonstrate decent agreement between our kinetic simulations and radiation hydrodynamics simulations in terms of macroscopic plasma parameters. We also discuss the role of the kinetic effects in EUV and next-generation BEUV sources.

Importance Sampling methods allow to substantially reduce the number of trials in estimation of the rare failure probability or other stochastic metrics. These methods can be viewed as a rigorous generalization of quantitative “torture” or “stress” methods where the process is artificially modified to increase the probability of failure, and the failure probability estimations obtained for such modified process are extrapolated to the original process with rare failures. Applications of Importance Sampling methods are presented and demonstrated on computationally efficient estimations of via failure probability and via LCDU. The accuracy of the Importance Sampling LCDU estimates is verified by comparison with experimental results. Applications of Importance Sampling methods to experimental measurements are discussed.

The pattern size of semiconductor circuits has been shrinking as technical advances continued. Defect control becomes tighter due to a decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra-high density pattern of sub – 20 nm tech devices. In this paper, we introduce two different types of process defects: one of the defects think related to mask blank surface status and the other defect may relate to etching chamber inner surface condition. By the experiment results, we will bring forward the possible defect generation mechanism. Based on this understanding, an appropriate solution by surface treatment methods to mitigate defects will be proposed.

State-of-the-art nanolithography machines employ extreme ultraviolet (EUV) light to pattern nanometer-scale features on silicon wafers for the production of integrated circuits. This radiation is generated in a laserproduced plasma formed on tin microdroplet targets. In this contribution, we give an overview of our recent experimental and theoretical studies on the properties of tin plasmas driven by short-wavelength lasers and the subsequent tin fluid dynamics. First, we will present a comprehensive characterization of the properties of laserproduced tin plasmas driven by lasers with wavelengths in the 1–10 µm range. Second, we present absolutely calibrated, charge-state-resolved measurements of the ion kinetic energy distribution recorded under multiple detection angles. Through extensive radiation-hydrodynamic simulations of the plasma formation, growth and expansion, we demonstrate that a single-fluid approach accurately reproduces the angular dependence of the ion energy distribution. Moreover, we identify the origin of a high-energy peak in the distribution as a high-speed shell generated at early times in the expansion. Finally, we show that the time evolution of the droplet target morphology is entirely determined by the early-time plasma-driven pressure impulse on the droplet.

The semiconductor industry has deployed EUV for the latest technology nodes, but the mask making limits have not scaled linearly with the wavelength. Characterization of the tradeoff between ideal placement of subresolution assist features (srafs) versus mask rule constraints (MRC) is needed. In this paper, a simulation study was performed with DUV, low NA EUV, and high NA EUV models on 1D patterns. Using systematic variation, the ideal width and pitch of the primary sraf was identified according to multiple metrics, Image Log Slope (ILS) and process variation (PV) band width. For DUV, optimum sraf placement maintains a large margin between the MRC limits and the sraf printing threshold. However for EUV, the ideal sraf likely violates the MRC minimum width. This is especially true for high NA EUV operating at a low aerial image threshold (AIT), where the ideal sraf width for ILS is only 2 nm. This paper quantifies the degradation in litho quality with the enforcement of increasing MRC limits. Alternative sraf insertion by chopping long srafs into minimum length srafs is applied to prevent sraf printing at MRC valid dimensions, while maintaining improved litho quality over no sraf.

During plasma excitation of CO₂ molecules in drive lasers, up to 60% of the CO₂ decomposes into CO. Typically, Au is used as a catalyst to preferentially recombine CO and O radicals into CO₂. By adding a secondary, microwave driven plasma to the system at the Au catalyst, O atoms can be stripped away from contaminants created in the laser such as O_x and NO_x compounds. It is hypothesized that this will decrease the CO:CO₂ ratio, which increases overall laser efficiency. This work serves as a status update on the measurement of CO:CO₂ ratios for 4 tests: 1) control, 2) with Au catalyst installed, 3) with secondary plasma active, and 4) with Au catalyst installed and secondary plasma active.

SMO sources with pupil fill values as low as 0.15 are targeted for use in High-NA EUV imaging to deliver improved NILS and contrast. These condensed source shapes in combination with high energy sources using 13.5nm light are placing ever increasing photo intensities onto EUV lens and masks. Furthermore, the highly focused diffraction energy of line space and contact patterns results in beam fluences that over time, may cause the multilayer performance to drift from the ideal. In this work a method for predicting imaging impacts in the high-NA, low pupil fill regime for simulated multilayer mirrors is presented.

The laser produced plasma of Extreme Ultraviolet (EUV) sources create energetic tin ions. Hydrogen buffer gas is used to slow down the ions through scattering. The scattering cross sections are not well known and are key to modeling the device. Beam attenuation experiments of tin ions in molecular hydrogen gas are underway in order to determine its effective cross section and intermolecular potential. This can be used to model tin ion transport inside of EUV source tools. Measurements are still underway and the exact values of the interatomic potential will be the topic of future publications. Once the potential is well characterized, it will be added to the open-source binary-collision-approximation code RustBCA.

The semiconductor industry faces numerous sustainability and environmental challenges. These include waste and the circular economy, water use, air pollution, global climate change, and energy use. These topics are interdependent. Many processes use process gases that have significant embodied energy. Recovery and recycling of these gases not only reduces operating costs and improves supply chain resilience, but also reduces the total carbon footprint of the process. To this end, Edwards is developing a Hydrogen Recovery System (HRS) capable of recovering EUV process waste hydrogen gas. The HRS purifies and pressurizes the waste hydrogen to meet purity & pressure requirements and recycles the gas directly into the EUV lithography tool. In partnership with imec, Edwards has demonstrated successful recycling into the ASML NXE:3400B EUV scanner installed at imec. Over 9 million standard liters (approximately 850 kg) of hydrogen have recycled with no negative impact to the performance of the EUV scanner, while reducing EUV-related hydrogen consumption approximately 70%. Recovery rates and purity are discussed.

Improving local critical dimension uniformity (LCDU) is always significant for enlarging process windows and reducing defect rates in lithography, especially for more scaling sub-20nm nodes in DRAM devices. In this study, various strategies are evaluated to improve both ADI and AEI LCDU on one of multiple patterning processes, Litho-Etch-Litho-Etch (LELE) process. Firstly, different advanced photoresists and track recipe optimization methods are explored and evaluated. The best result shows ADI LCDU is improved by 10.0%, and AEI LCDU by 10.3%. Secondly, several source mask optimization (SMO) solutions are tested and ADI and AEI LCDU is improved by 5.5% and 5.7%. Thirdly, new type of photomask, 30% high transmission phase shift mask (HT PSM), is introduced to optimize NILS and MEEF performances. The result shows ADI and AEI LCDU are enhanced by 13.7% and 14.2%. Additionally, etch advanced vertical profile approach can further improve on-device AEI LCDU by 19.0%.