This PDF file contains the front matter associated with SPIE Proceedings Volume 12495, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

It is well known that the computations required to manufacture semiconductors have been increasing exponentially. Optical Proximity Correction has so far consumed the largest share of a fab’s compute cycles, but other kinds of calculations, for example during inline inspection, have also been growing steadily. With the relentless march of technology nodes, we have had to squeeze increasingly complex Physics into a limited compute envelope, due to which simplifying assumptions made for one technology node tend to become invalid at the next node. Accelerated computing solves this problem in two different ways – by drastically reducing the cycle time for increasingly complex calculations, and by freeing up the compute envelope to allow the incorporation of previously prohibitive physical effects or compensation. The other trend that is sweeping all manner of computations in the world today – from search to scientific simulation – is the increasing reliance on AI, and silicon manufacturing is no exception. This talk will describe these larger trends towards Accelerated Computing and give examples of how its use in silicon manufacturing will likely be required for the fastest time to market.

In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.

The original inverse lithography technology (ILT) commitment of creating a free-form mask from ex nihilo underwent transformation under pressure of constraints that are imposed by the capabilities of manufacturing and inspection equipment. This pressure became especially noticeable in the dealing with sub-resolution assist features (SRAF). The freeform SRAFs are naturally unmanufacturable and hard to inspect. In addition to this complication, the ILT signal for SRAFs is substantially weaker and often ill-defined in comparison to a strong signal from fidelity objectives to print main features on target. So, it is difficult to automatically produce SRAFs that are simultaneously geometrically stable, do not print, MRC-clean, and deliver the best lithographic quality. To overcome these obstacles, we propose new concept of structured SRAFs by combining ILT ideas with robust geometrical parameterization to introduce well-behaved and MRC-clean by construction mask decorations.

The edge-based OPC has been serving the industry for more than 20 years with few changes in the way to alter the mask. In the past 10 years, ILT pioneers in the creation of the curvilinear mask using alternate algorithms. The two approaches differ so much that the experiences in conventional OPC do not easily translate to the use of ILT and vice versa. In this paper, we report a new system for curvilinear OPC built on top of the conventional OPC workflow without being limited to moving edges. It creates and manipulates the curvilinear shapes by generalizing the edge-based OPC to vertices. Conventional OPC techniques, including dissection, classification, target point placement, etc., keep playing central roles. Full-chip correction results demonstrate the good performance of the curvilinear mask for both contact and line/space patterns. The runtime cost of adoption is reported.

As the industry is developing curvilinear mask solutions, some curvilinear post-OPC masks have been reported with file sizes in excess of 10 times the corresponding Manhattan post-OPC files, which can greatly impact mask data storage, transfer and processing. Some file size reduction utilizing spline fittings has been reported in mask post-processing. However, from an OPC perspective, mask post-processing is undesirable. In this study, we show that maintaining an adequate density of mask control points (MCPs) is key to achieving the desired on-wafer lithographic performance, regardless of whether the MCPs are connected by spline sections or piecewise-linear segments. Our results suggest that) may not offer clear lithographic performance or file size benefits. We will also offer some guidance for controlling piecewise-linear file size without compromising lithographic performance.

Multi-beam writer endowed photomask manufacturers a freedom in curvilinear design without concern for photomask write time. However, a similar concern is now happening in edge-based Mask Process Correction (MPC). When curvilinear pattern gets MPC, the number of figures tend to increase dramatically and takes longer time to process, just like VSB writer experienced shot count and write time increase before. NuFlare Technology Inc. has been developing inline, pixel-based MPC software and hardware embedded on multi-beam writer. This paper describes how our inline, pixel-based MPC achieves pattern fidelity enhancement and zero additional turn-around-time at the same time.

The technological demands on the semiconductor industry continuously require shrinking feature critical dimensions (CDs) and improved feature CD control. To meet feature CD demands requires advances in DUV and EUV lithography as well as improvements in photoresists, including negative tone-development (NTD) and positive tonedevelopment (PTD), materials properties and processing. As an example, the semiconductor industry has benefited from significant improvements in 193nm lithographic resolution and process window with NTD photoresist (resist) patterning processes of trench and hole/via features. Consequently, optical proximity correction (OPC) compact modeling of NTD resists has needed to advance to accurately model the different chemical and physical material properties, including the deformation, of thin films. From a fundamental point of view, while the basic deformation and shrinkage behavior observed in NTD resists is captured by rigorous and compact simulators, there remains known complex phenomena, such as polymer entanglements, strain softening, and strain hardening, in the materials science community, that are not present in the current models applied in OPC. In this paper, we describe these phenomena and, where appropriate, their impact on compact and rigorous resist modeling. Finally, we discuss how these newly addressed deformation effects may improve overall OPC accuracy and therefore enable further feature CD reduction and control.

As chip manufacturers seek to reduce the pitch of metal layers, there is growing interest in replacing the multiple patterning process of 0.33NA EUV with a single patterning of high NA (0.55NA) EUV. However, to resolve a logic metal layout with a minimum pitch of 20-24nm, careful use of resolution enhancement techniques (RETs) and SMO (source mask optimization) is required in high NA EUV. Logic metal patterns are complex and have various feature designs, making it essential to ensure sufficient patterning performance across all pitches and for variations of tip-to-tip (T2T) structures with a tight size. In this study, we simulated and evaluated patterning on a typical logic metal layout representing 1.4nm to 1nm technology nodes. Our study demonstrates that compromised criteria are necessary to ensure the NILS (normalized image log-slope) level of the minimum pitch and the overlap critical dimension (CD) process window (PW). In optical proximity correction (OPC), sub-resolution assistant features (SRAF) help to improve the process window of isolated and semi-iso line-and-space (L/S) patterns. However, we found that the limiting patterns are the tight T2T structures. Aberration sensitivity showed a linear response that is more pronounced to pattern placement errors (PPE) than to CDs. The coma series aberration showed the highest sensitivity to PPE and CD. Overall, our study demonstrates that RETs, rigorous SMO solutions, and a minimum T2T size are required to achieve the replacement of 0.33NA EUV multi-patterning with a 0.55NA EUV single patterning (SP) for logic metal layers with minimum pitches of 20-24nm.

Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].

The first high-NA EUVL scanner will have an 0.55 NA and will use anamorphic magnification. Therefore, the standard 10×13 cm lithography mask will be imaged into a 2.6×1.65 cm rectangle on the wafer due to the increased reduction factor of the lens’ vertical direction. Layers exposed on high-NA anamorphic scanners will require two stitched halffields to achieve the equivalent exposure area of previous-generation scanners. Stitching strategies will depend on the product type being manufactured. For chips with a large die area, it will be necessary to stitch fields across the die. For smaller chips, it may be advantageous to use three stitched exposures depending on the die size. In any case, the stray light from neighboring fields and black border proximity effects cause challenges for robust manufacturing. Some recent studies have shown that the CD may vary significantly as a function of the proximity to the black border edge due to multilayer stresses. In addition, stitching through a die has increased optical proximity effects which will need to be corrected to achieve the desired wafer CD. In this paper we examine the effects relevant to designing a stitched process, quantify manufacturing tolerances, and show how these effects can be corrected with EDA. More specifically, we examine the optical and mechanical properties of the multi-layer black border etch and optimization of sub-resolution gratings to reduce reflectivity with phase shifting absorber materials. Ultimately, we will show that for a well designed stitch, the effects of stitching can be corrected without impact to process window.

Extreme ultraviolet (EUV) double patterning (DP) with a numeric aperture (NA) of 0.33 can be introduced for the critical via layers at 3nm logic node. The minimum center to center (C2C) distance of a via pattern may form bridging defects even adopting EUV DP. The implemented via process, pattern shifts induced by EUV illuminator, overlay capability and OPC strategies may lead to bridging defects in EUV DP process. This paper will put forth a compact model to detect potential bridging hotspots and predict the corresponding probability of failure considering aforementioned process variations. The feasible design, patterning solutions, and process parameters can be optimized and compensated quantitatively to avoid design updates and mask rebuild.

This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of ~30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers. Careful co-optimization of the illumination source, photoresist and lithography stack is essential to resolve the tightest pitches. Optimum CDSEM metrology conditions and EUV specific requirements such as full field correction with thru slit, flare and black border compensation are critical to improve the quality of the optical proximity correction (OPC) flows. OPC algorithms were used to maximize the process window by using width sizing and pitch shifting to meet lithographic printability criteria while pushing mask manufacturability constraints to their healthy limits. The sizing of metal lines is modelled and fed to the RC extraction flows to close the fabdesign house feedback loop to improve accuracy of timing closure. A novel directional etch process enabled the direct print patterning of line tip-to-tips without requiring a second blocking mask. Multiple test masks were specifically designed to increase sensitivity of defect metrology and accelerate yield learning. Our results from multiple product vehicles demonstrate achievement of technology readiness milestones.

The introduction of the multi-beam mask writer has made it possible to introduce non-Manhattan shapes on photomasks with no write-time penalty compared to the standard rectilinear mask shapes. While it has been known for some time that removing the Manhattan restriction on OPC output not only allows for improved process window, more recently it has also been demonstrated that it improves mask CD uniformity (CDU). When crucial mask rules are followed, most notably a minimum allowable curvature, we assess the CDU changes at the mask level for an MRC-constrained correction, as compared to either Manhattan or unconstrained corrections. An AIMS analysis was performed to estimate the effect at the optical plane. Lastly, we contrast differences in the CDU as transferred to resist in EUV lithography. We conclude with a view as to the challenges left to enabling high-volume manufacturing of all-angle shapes.

Modern semiconductor design to fabrication process mainly relies on intra-module validation mechanism to prevent the propagation of systematic defects, such as DRC signing off physical design, OPC Verification validating OPC solution, metrology and inspection gauging the process, and physical failure analysis confirmation of electrical diagnosis. The inter-module information exchange and co-optimization typically happen during the early process and technology development stage via Design-Technology Co-optimization (DTCO). Later into the advanced node’s lifecycle, such co-optimization is facilitated by traditional techniques like Design For Manufacturability (DFM) and Litho Friendly Design (LFD). This talk will present methodologies and infrastructure necessary to feed pre-silicon design data and intelligence forward into the manufacturing process and feed manufacturing information back, post-silicon, to inform the design process.

NAND flash memory has wide applications, from mobile phones to data centers. There is an insatiable need for Flash storage. NAND is the most exciting semiconductor memory around with continued scaling. The capital intensity and competitive landscape continues to fuel many innovations in flash architecture and its applications. This talk will give a brief introduction to NAND architecture changes in 3D NAND flash as it continues its aggressive physical scaling by growing more layers. NAND scaling is expensive and capital efficiency is one of the key metrics to be considered. There are many innovations in 3D NAND architecture, with the ongoing drive to shrink die size and drive the NAND roadmap for the future. On the application side, we will look at zone named space (ZNS), a new system architecture that reduces the “wear and tear”on flash memory and which also helps adaptation of 4 bits per cell (QLC) in SSD.

Free-form ILT has the best lithography quality but suffers long runtime and large file sizes. The shortcomings can be mitigated by using spline-polygon curvilinear mask. Further more curvilinear OPC can be used to drive down the EPE, further improving the runtime and correction quality

Curvilinear layout data has been used for better mask quality for ILT OPC results, but it has issues such as complexity, huge data volume and absence of established verification methods. In this presentation, fundamental and practical verification methods will be discussed for complicated curvilinear geometries. On top of that, real curve data (parametric curves) has been discussed to reduce the mask data volume. The MULTIGON record has been defined as the real curve expression. We will explain the characteristics of the new record and show the outlook about how the mask industry should deal with its complexity.

With the adoption of multi-beam mask writing (MBMW) technology, there is a strong drive to realize the maximum lithographic process window entitlement which can be obtained with curvilinear masks, including both SRAFs and main features. Inverse Lithography Technology (ILT) has always featured prominently in planning for such masks, as it can produce the ideal curvilinear patterns which represent the best possible solution. The runtime for ILT, however, remains too slow for full-chip logic manufacturing and this paper will review multiple alternative approaches which endeavor to produce similar output masks but with significantly faster runtime. Results will be shown for 3nm-node via and metal examples where full ILT, hybrid ILT and dense curvilinear OPC, hybrid curvilinear SRAF and dense curvilinear OPC, and machine learning approaches will be assessed for runtime and a variety of lithographic metrics. Overall, all solutions are shown to be considerably faster than full ILT, ranging between 4x (for hybrid ILT SRAF) to <100X improved runtime performance. Lithographic capability is characterized in terms of distributions of edge placement errors (EPE), PV Bands, and ILS/NILS. There are some minor differences between the various options, but given the pronounced runtime advantages over ILT, all are compelling options, delivering lithographic PW enablement close to the ideal ILT solution. For the model-based DNN, and Monotonic Machine Learning (MML) approaches, we will discuss the approach, challenges, and advantages associated with robust training to ensure the broadest possible pattern coverage.

Vertical-Transport (VTFET) Nanosheet Technology is an attractive solution to enable aggressive CMOS scaling in the sub-45nm contact-gate-pitch (CGP) regime. By decoupling the classic tradeoff of S/D contacts, gate length & contact-gate-pitch (CGP), VTFET technology overcomes middle-of-the-line (MOL) dominated performance pinch-points by providing independent optimization of the contact dimension & device width as well as significant effective capacitance (Ceff) reduction [1]. VTFET offers an attractive solution at sub-45nm CGP, however it introduces unique design challenges that need to be optimized to take full power-performance-area (PPA) entitlement. In this paper, we present for the first time a logic standard cell architecture to enable a competitive VTFET technology. First, we introduce key features of the VTFET architecture which enable significant advantages relative to leading-edge competitive technologies. Further we describe key Design Technology Co-Optimization (DTCO) scaling knobs that naturally lend themselves to VTFET such as single fins, buried power rails and gate-contact super vias can achieve competitive area scaling vs. an industry 7nm lateral FinFET transistor reference. Finally, we draw conclusions of overall PPA benefits of this technology.

Fin depopulation, thinner and taller fins, and the step towards Nanosheet technologies has been helping in maintaining the rhythm of the semiconductor technology roadmap. Nevertheless, further area scaling causes a drastic reduction in active width as well as a challenging routability. On this regard, the Complementary-FET is a strong contender as device for next generation technologies. The stack of p- on n-FETs offers several opportunities for device scaling and optimization. However, it also poses several challenges that need to be carefully analyzed in a design-technology cooptimization framework.

For nanoimprint lithography (NIL), computational technologies are still being developed. Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their everyday toolbox. In this paper, we introduce a new NIL process simulator which simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale difference of each component of the system, which makes it difficult to calculate the process with conventional fluid structure interaction simulators, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region.

Computational lithography is a critical research area for the continued scaling of semiconductor manufacturing process technology by enhancing silicon printability via numerical computing methods. Detailed topics include lithography modeling, resolution enhancements, optical proximity correction (OPC), and source mask optimization (SMO). In this work, we focus on 1) lithography modeling, which computes the post-lithograph shape on the silicon wafer given a mask design; and 2) mask optimization (inverse lithography), which optimizes a mask design such that the remaining pattern on the silicon wafer after the lithography process is as close as possible to the desired shape (\Cref{fig:intro}). Today’s solutions for these problems are primarily CPU-based and require many thousands of CPUs running for days to compute the masks required for a modern chip. We seek AI/GPU-assisted solutions for these two problems, aiming at improving both runtime and quality.

EUV lithography has been ramped to successful volume manufacturing through a combination of improvements in process technology, layout design and device interactions, and also optimization of the overall product integration to reduce undesirable interactions. Because EUV has additional sources of systematic and stochastic variation that did not exist in DUV lithography, it is now even more important to have accurate predictive capability to test and understand the design and lithography process interactions. EUV-specific physical behavior such as shadowing, flare, mask topography (i.e., Mask3D) effects, mask stack reflectivity, mask absorber behavior and other effects are key differences in how EUV forms an image on the mask and subsequently on the wafer. The reflective mask substrate and EUV-specific mask absorber stack are therefore highly important technologies to optimize as the industry pushes both low NA (0.33NA) and high NA (0.55NA) technologies to cover the patterning requirements of upcoming 3nm and below technology nodes. Recently there have been substantial industry interest in optimizing EUV mask stacks to further enhance imaging behavior and achieve better pattern resolution, increase process window, lower stochastic defectivity and optimize flare. Several different options have been proposed for these new EUV mask stacks for lower K1 EUV patterning. All of these new options require excellent simulation accuracy in OPC, SrAF placement, OPC verification and ILT mask synthesis steps in order to realize the benefits of the new mask stacks. In this paper we will focus on analyzing and improving the accurate prediction of a range of new EUV mask stack options for full-chip OPC/ILT compatible compact models. We will show for advanced mask designs the accuracy requirements and capability of leading-edge compact models. The accuracy requirements and capability will be referenced to fully rigorous electromagnetic solver (e.g., Mask3D) results to ensure industry needs are met. We will also explore the mask stack options to highlight the imaging benefits for different material thickness, refractive index (n) and extinction coefficient (k) on important mask pattern feature and layer types.

For advanced technology nodes, leading edge mask fidelity is ensured by applying a mask error correction (MEC) solution that mitigates the distortions caused by the many proximity effects present while manufacturing these masks. The centerpiece of the MEC solution is a compact model that captures these systematic effects and allows the accurate prediction of the printed signature on the mask for any layout slated for the process in consideration. In addition, time and resources constraints at the fab dictate that the model must be efficient enough to make the actual step of correcting the mask a fast and practical one. The introduction of advanced modeling schemes based on machine learning is providing new dimensions for the exploration of this perennial balance between accuracy and speed, including in the context of lithography mask models. This has been a focus of development at Synopsys as multiple routes have been implemented, with promising outcomes for mask model accuracy and correction turnaround time (TAT) performance. This paper provides examples of the improvements as well as comparisons between the different approaches, showing how deep learning can be leveraged to significantly increase mask model accuracy while keeping simulation and correction TAT within acceptable limits.

The EUV High-NA scanner brings innovative design changes to projection optics, such as introducing center obscuration and the anamorphic projection optical system in the projection optics box (POB) to improve the system transmission while the NA is improved1 . These design changes need to be accounted for in the computational lithography software solutions, to ensure accurate modeling and optimization of the High-NA system performance on wafer. In this paper, we will systematically investigate the benefits of Source Mask Optimization (SMO) and mask only optimization to explore EUV High-NA full chip patterning solutions, where mask 3D effects (M3D) are captured in the optical modeling. The paper will focus on assessing the performance (including process window, depth of focus, normalized image log slope) of through-pitch 1D Line/space (L/S) patterns and 2D Contact/Hole (CH) patterns after aforementioned optimizations and demonstrate the impact of center obscuration on imaging. In addition, we will investigate the effect of sub-resolution assistant feature (SRAF) on High-NA patterning via comparing the optimized lithographic performance with and without SRAF. These findings will help determine the most optimal patterning solutions for EUV High-NA as we move towards the first High NA EUV insertion. The paper will also discuss the anamorphic SMO where MRC and mask description needs to change from wafer plane (1x1) to scaled reticle plane (1x2). The interfield stitching will also be briefly discussed in this paper.

This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm²) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.

As the semiconductor manufacturing technology node scales down in the deep submicron domain, hotspot detection becomes more challenging and geo-contextually dependent than ever before. The need to profile IC layout patterns based on geometrical commonalities becomes a significant demand either during IC layout design or manufacturing phases. Identified hotspots during the manufacturing phase are usually correlated to specific geometrical configurations sensitive to the lithography process or other manufacturing processes. Accordingly, identifying similar geometrical configurations is an important step toward locating potential hotspots. Once these hotspots are identified, their patterns can be provided to the router to avoid using these patterns and find other valid alternatives. Furthermore, in the IC design sign-off phase or Design Rules Check (DRC), layout profiling can identify patterns with high commonalities to these problematic patterns that potentially lead to a yield loss. In this paper, we introduce automated IC layout patterns topological profiling approach using Directional Geometrical Kernels (DGKs) to capture the context of patterns around a Point-Of-Interest (POI) in an IC layout, such as a hotspot. The DGKs pattern representation provides a direct one-to-one mapping with physical geometrical measurements centered by the POI and doesn’t need further feature extraction models or maps used by other pixelized gridded imagebased or density-based representations, which are both time and computational resources-consuming. The DGKs are decomposed into topological and dimensional components. This makes the mechanism of patterns topological profiling not in need of complex models and can be precisely fine controlled to produce adequate patterns profiling granularity that is not easily approached by other patterns profiling alternatives.

Power delivery represents a key challenge in scaled technology nodes as interconnect wiring resistance increases and design constraints impact how much wiring can be used for power distribution. Here, we discuss several methodologies, including both pre-PDK and post-PDK, to benchmark the integrity of power delivery network designs with advanced technology features such as vertical FET (VTFET) transistor architecture, skip-level vias, buried power rails and backside power delivery. For a post-2nm node VTFET architecture, we employ a pre-PDK benchmarking to find that buried power rails can reduce gate delay by as much as 30%. For 5nm and 2nm technology nodes, we use existing PDKs to simulate backside power delivery networks (BS-PDN) and find that scaled logic area can be reduced by 10-30% while minimum-pitch interconnect RC delay can be reduced by as much as 70% depending on reference design.

Design for Manufacturability (DFM) in-design fixing methodologies are developed to improve Manufacturability Aware Scoring (MAS). Two methodologies have been evaluated. For the first methodology, DFM recommended rules are inserted in the reference flow for rip-up-and-reroute, thus fixing DFM rule violations, improving the MAS score. For the second methodology, pattern classification is used to classify the recommended rules into patterns based on the profiling of multiple layout designs. A library of fixable patterns with corresponding fixes is built. The pattern library is then inserted in the rip-up-and-reroute flow to fix the DFM rule violations, improving the MAS score. The methodologies are demonstrated on 28nm technology. Results show an average fix rate of 89.1 % for a design with a core utilization of 0.6 and 78.4% with a core utilization of 0.6 for three DFM MAS enclosure rules, VIA2, VIA3 and VIA4 layers.

Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.

For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.

Fine-pitch 3D integration is considered a promising way to advance traditional CMOS scaling as 3D interconnects are currently capable to match the connectivity among functional sub-blocks of a system, enabling their displacement on different tiers. A major bottleneck for 3D ICs is represented by the power delivery, due to the challenge of supplying multiple dies. This work aims to provide insights into the system-level impact of PDN in a 3D chip, in terms of frequency and IR drop. A highly-interconnected memory-dominated SoC is physically implemented using the same 2nm technology in 2D and 3D. For both options, the results are compared with an ideal PDN-less implementation, showing that 3D-induced frequency (up to 9.3%) and wirelength (∼ 10%) benefits are retained upon PDN insertion. From the power integrity perspective, a ∼ 60mV dynamic IR drop improvement is observed in 3D, compared to a conventional frontside PDN in 2D, when considering the 90th percentile of a cumulative distribution function. This work validates the expected technology-driven benefits of 3D integration at the system physical design level, in a realistic environment including a 3D PDN.

Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.

Technology evaluation of new nodes is becoming increasingly complex; where transistor performance was once the critical metric, technology evaluation currently requires more complex metrics such as AC power and area. We present a method to utilize Synopsys TCAD to generate HSPICE collateral from device and process simulation to enable circuit simulation. This workflow is automated to support generation of packaged standard cell library collateral, enabling early analysis of more complex circuits which utilize automated routing tools to create. This workflow enables a much more accurate and complete picture of technology performance in a faster way than traditional PDK-based workflows.

The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging. Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs. A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to address die fracture from both the front and the back sides of the wafer, yielding an authentic 3D approach to crack-stop.

In modern digital integrated-circuit designs, standard-cell libraries are key foundations. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. In this work, as a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristics deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade standard-cell optimization.

After large yield limiters are addressed during ramp, subtle layout pattern systematics continue to cause physical defects and prevent achieving entitlement throughout volume production of semiconductors. Current approaches are insufficient and require layout and location specific fallout information to further inform the pattern analysis engine. In this presentation we will describe a new approach to combine a pattern analysis engine (FIRE from PDF Solutions) with volume logic scan diagnosis (RCD from Siemens). The resulting yield Paretos include specific layout pattern systematic families as distinct root causes and show an overall increase in defect Pareto accuracy from ~70% to ~90%.

Logic diagnosis attempts to identify defects within an Integrated Circuit (IC) using only a logical model of the design with no knowledge of the physical layout. With the ever-increasing size and complexity of ICs, limitations associated with traditional logic-based diagnostics have made it less effective at determining root causes for failing die. To provide increased a

The growth of applications in the automotive space including safety, security, driving assist, vehicle dynamics, networking, etc. is driving exponential demand for superior quality semiconductor products in the vehicle. This carries a serious responsibility for suppliers, as automakers expect quality that can be measured on a defective parts per billion scale (DPPB). Orthogonal to this is the continued aggressively shrinking technology roadmap supporting the new advanced finFET nodes, where exponentially complex processing is creating limitations in Design for Manufacturing needed to achieve Zero Defect products. Additionally, increased product complexity and higher number of product features can lead to lower observability requiring new thinking to detect, accelerate, and prevent escape. This paper explains the challenges and new solutions to delivering products at these strict automotive required intrinsic and extrinsic quality levels, all while at an acceptable product cost. Using real world case studies, it highlights advances in innovative test methods deployed to target “time zero” (T0) random and systemic defects, and Design for Stress and Advanced Outlier Detection techniques used to activate, then screen potentially “latent defects” during factory testing. The paper illustrates why there is no single silver bullet that can deliver ZD product quality in advanced nodes, instead it is necessary that industry experts from fields such as process technology, design, product, test and quality teams, collaborate on and co-deliver complementary process, design and test solutions to achieve the ever-increasing demands for quality in the industry.

This paper presents a novel methodology called Design-for-Inspection (DFI) that enables sensitive inline pickup for failure mechanisms previously undetectable until product test (wafer sort, final test, HTOL) or field failures. Dummy filler cells are replaced in the physical design flow by DFI-enabled filler cells which are designed to be sensitive to specific failure modes without any area penalty. To achieve very high inspection throughput, we have developed a proprietary vector scanning eBeam Voltage Contrast tool called eProbe 250 which is capable of inspecting up to 5 billion Devices Under Test (DUT) per hour. Due to novel processing of gray levels the system is capable of detecting not only the hard defects such as shorts or opens, but also the soft failures, namely leakages and resistive contacts and vias. We illustrate this methodology by several examples from the most recent FinFET technology nodes.

Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.

This paper proposes a new methodology that can greatly accelerate Manufacturability Analysis & Scoring (MAS) deck runtime. The intention of this work is to provide a quick preview check to ensure that a new design will pass MAS signoff. Instead of running the deck on the full design, the input design is sampled down to a few random locations which are then analyzed. Furthermore, the actual MAS checks are replaced by an ML trained lookup methodology that keys off very simple design parameter like layer area density and layer perimeter density. The output of the deck is a simple PASS/FAIL statement and a range forecast for the MAS score based on a statistical assessment. We can demonstrate 4x runtime improvement while incurring minor tradeoffs for accuracy.

As the technology node scales down below nanometer, the design rules significantly increase, which in turn results in the huge search problems of the chip design with an early-stage technology. DTCO (Design-Technology Co-Optimization) becomes a key methodology in semiconductor industry to overcome the limitation of physical scaling and transistor density, and to improve performance and power efficiency [1-2]. However, DTCO induces huge increase of design spaces in physical implementation since chip designers should tune the technology related variables along with the conventional design variables at the early technology stage. ML (machine learning) is a powerful technique when tuning and optimizing such complicated parameters in technology and design [3]. Synopsys DSO.ai (Design Space Optimization AI) is an early innovator of ML (Machine Learning) in EDA (Electronic Design Automation) area, where the tool uses advancements of RL (Reinforcement Learning) to effectively search the massive design space for global near-optimal targets [4]. In this paper, we report DSO.ai applications on 3nm technology and designs, such as PPA (Performance-Power-Area) improvements in both HP (high performance) and HD (high density) libraries, NDR (non-default rule) routing on both clock and signal nets, LP (layer promotion), density control, routing wire and via cost tuning, and more. Furthermore, we utilize ML capability in searching and optimizing technology parameters, e.g., key design pitches and design rules, as well as design parameters, e.g., via/wire cost, placeholder densities, legalization and routing strategies, and other EDA settings, to maximize PPA metric and to minimize DRC violation. Our goal is to find the best values of the initial parameters from an early technology and design stages and to encapsulate them in RM (Reference Methodology) script to provide the designer with the mega switch in entire design flows. Parameter range (to be explored) and evaluation metrics (to score QOR) are defined, then DSO.ai explores search spaces and trains itself to minimize the optimization cost. Optimized parameter values are evaluated against the reference parameters to reproduce the benefit across various designs and technology collaterals. In this manner, different parameters can be optimized given design methodology. This iterative process can be extended to optimize all design technology parameters to maximize PPA on 3nm design technology and designs and beyond. Proposed approach applied to optimize achievable core area and improve max frequency, respectively. Design flow with ML-assisted parameter could reproduce improvement across the different size and different styles of the benchmark designs. Optimization for achievable core area could reduce -0.5% at cell-driven design and -0.6% at route-driven design. Optimization for performance could improve the frequency of +1.42% at cell-driven design and +1.43% at route-driven design in Samsung 3nm technology.

To successfully transfer design patterns to wafer, it is essential to calibrate different types of models to describe the optical, physical, and chemical effects in chip manufacturing process. In recent years, there have also been active investigations of machine learning (ML) models to capture various aspects of semiconductor processes. As it is well known, model training time and model accuracy are heavily influenced by the input data. It is becoming increasingly important to provide highly efficient methods to automatically generate effective pattern samples from full chip designs. A straightforward approach, simple random sampling, can be highly efficient to generate effective samples for a homogeneous population. However, real world chip layouts are characterized by geometrical and lithographical feature distributions that vary significantly across the full chip design space. The complexity of the problem necessitates the adoption of a comprehensive set of approaches for sampling as well as flexibility in customizing the sampling strategy for various applications. In this paper, we investigate automatic layout sampling to optimize the coverage and diversity of patterns given the need for minimizing training sample size or other constraints, and therefore adopting various unsupervised learning techniques. The flow scales very well with computation resources to efficiently process full chip layouts. A simple, standard interface is provided for typical usage, but flexible programming APIs are available to customize the sampling strategy for advanced applications. Results demonstrate that the samples generated by this flow have increased diversity, which leads to significantly reduced model training time with comparable or increased model accuracy.

The identification of process bottlenecks for emerging nodes is becoming critical in early technology pathfinding. This is chiefly due to the impact of many process parameters on scaling performance. Moreover, quantifying impact of process parameters on scaling performance is of utmost importance since that will determine the ultimate patterning pitches. Edge placement error (EPE) budget is a key limiter for scaling. Previously we introduced a Machine learning based analytics framework to perform impact analysis of various process assumptions on EPE. Here, we extend this framework to forecast key limitations of EUV double patterning for 2025 nodes and beyond. Following the adoption of EUV lithography, the industry is exploring increasing the numerical aperture (NA) to enable high-NA EUV processes. We apply our simulation framework to predict key process sensitivities for controlling EPE for high-NA EUV lithography.

Depth of focus reduction due to the increasing numerical aperture (NA) for High NA Extreme Ultraviolet (EUV) lithography and decreasing feature sizes of the latest process nodes necessitate smaller resist thicknesses. Reduced resist thickness degrades scanning electron microscope (SEM) image contrast significantly due to a lower signal-to-noise ratio (SNR). It is possible to improve SNR by changing the number of frames averaging or using higher resolution SEM images. However, these techniques limit high-throughput defect screening and can potentially impact the measurements due to electron beam damage. In this work, we present a deep-learning-based denoising method for sub-nm metrology. Power spectral density analysis of artificial intelligence (AI) reconstructed images shows the developed AI model is capable of denoising SEM images to provide comparable measurements such as line width roughness (LWR) that are only attainable with SEM images with higher SNR.

Machine Learning (ML) based technologies are actively being adopted in the computational lithography domain. ML-based methods have the potential to enhance the accuracy of predictive models, speed up the run-times of the mask optimization processes and produce consistent results compared with the other numerical methods. In this paper, we present the result of an ML-based ILT application to an advanced DRAM contact layer for both core and periphery region. In our ML ILT method, golden mask layouts are generated by ProteusTM ILT tool for the sampled target layouts to obtain reliable training inputs, which are then used to train a custom-designed Convolutional Neural Network (CNN). The trained CNN is plugged-in to the conventional ILT flow as an initial mask provider and the entire

Optical proximity correction becomes more and more critical since the technology nodes shrinks nowadays. It usually costs a lot of computational power and days are needed to finish this process. Increasing its speed has become an important research topic. Machine learning technology has been applied to achieve this goal. Generative modelling such as generative adversarial networks appears to be beneficial and applicable in doing the optical proximity correction. We prepare the paired target layout and post OPC layout. The target layout is input into the U net type generator and its output is the calculated post OPC layout. The calculated post OPC layout and corresponding post OPC layout are input into the discriminator of the generative adversarial networks. The discriminator is trained to maximize the discriminative loss function, while the generator is trained to minimize the discriminative loss function. When the whole conditional generative adversarial networks converge, the generator can generate the calculated post OPC layouts quite similar to the prepared ones. The generalization capability of the deep neural network is important here. The generator can also provide good post OPC layout for unseen target layouts. However, the training of generative adversarial networks is difficult and often unstable. To improve this, we use Wasserstein distance as the loss function and stabilize the training and convergence of the conditional generative adversarial networks. We can obtain better results easier this way.

Design for Manufacturability (DFM) physical verification checks using supervised Machine Learning (ML) are developed and optimized to identify via-metal enclosure weak points to prevent via opens caused by line-end shortening post-retargeting. Various methods for generating feature vectors and neural network architectures are evaluated for optimizing training time and ML model quality. Techniques include applying PCA to image-based density vectors generated from layout clips to identify the principle components or using localized layout features directly for model training. Results show that for a sample size of 300k vias, the image-based density vectors versus localized layout feature vectors achieve similar correlation coefficients of 0.95 and normalized RMSE of 0.11, with a training time of 10+ hours versus 1+ minute, respectively.

The development of optical devices requires the patterning of non-conventional shapes on the wafers [1,2,3,4,5]. In addition to the specific challenges related to the treatment of these curvilinear patterns, an accurate proximity correction must be provided. The Critical Dimensions (CDs) of such patterns are indeed around 100nm, which requires the implementation of advanced lithography processes, similar to CMOS microelectronics technologies. In order to develop a production compliant and robust OPC solution, we previously demonstrated the need for etch bias modelling [1]. Taking the example of optical metasurfaces application, and using ASML’s Tachyon OPC+ platform, we will present the implementation of an OPC flow suitable for curvilinear patterns, starting from the metrology strategy. We will then discuss the etch model calibration methodology, model-based etch bias correction implementation in OPC, and global OPC performance.

Numerous recent approaches have proven the efficacy of deep learning as a fast and efficient surrogate for various lithography simulation use cases. However, a drawback of such approaches is the requirement of large amounts of data, which is often difficult to obtain at advanced nodes. Different means to alleviate the data demands of deep learning models have been devised, such as transfer learning from different technology nodes and active data selection. Active data selection techniques tend to require large amounts of data to optimize and select. In our previous work, we devised a more efficient implementation of transfer learning and detailed numerous applications for EUV lithography. In this work, we expand on the data efficiency enhancements with domain knowledge-based data selection and the use of alternative data generated by different modeling approaches.

Mask 3D effects distort diffraction amplitudes from EUV masks. In the previous work, we developed a CNN which predicted the distorted diffraction amplitudes very fast from input mask patterns. The mask patterns in the work were restricted to Manhattan patterns. In general, the accuracy of neural networks depends on their training data. The CNN trained by Manhattan patterns cannot be used to general mask patterns. However, our CNN architecture contains 70 M parameters, and the architecture itself could be applied to general mask patterns. In this work, we apply the same CNN architecture to mask patterns which mimic iN3 logic metal or via layers. Additionally, to study more general mask patterns, we train CNNs using iN3 metal/via patterns with OPC and curvilinear via patterns. In total we train five different CNNs: metal patterns w/wo OPC, via patterns w/wo OPC, and curvilinear via patterns. After the training, we validate each CNN using validation data with the above five different characteristics. When we use the training and validation data with same characteristics, the validation loss becomes very small. Our CNN architecture is flexible enough to be applied to iN3 metal and via layers. On the other hand, using the training and validation data with different characteristics will lead to large validation loss. The selection of training data is very important to obtain high accuracy. We examine the impact of mask 3D effects on iN3 metal layer. Large difference is observed in T2T CD calculated by thin mask model and thick mask model. This is due to the mask shadowing effect at T2T slits. Our CNN successfully predicts T2T CD of thick mask model, which is sensitive to the mask 3D effect.

The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.

As the semiconductor process technology steps into a more advanced node, design and process induced systematic defects become increasingly significant yield limiters. Focus Exposure Matrix (FEM) method is crucial for early detection of these defects. However, analysis of a typical FEM wafer which contains half million of defects requires extensive time and efforts. In order to improve FEM wafers review efficiency, we introduce a smart review point selection strategy based on different layout pattern grouping modes. This review point selection strategy enable engineers to sample the more effective defects for SEM review.

Lithography hotspot detection is a key step in VLSI physical verification flow. In this paper, we propose a hotspot detection method based on new data augmentation, residual network and pretrained network models. The residual network preserves the depth of the deep convolutional neural network while taking the advantages of the shallow network, thus avoiding network degradation and improving the learning ability of hotspot features. We also apply data augmentation methods to increase the number of hotspot samples, so that the model can be trained with balanced data and prevent neural network overfitting. Our research shows that the proposed network’s improved performance and efficiency over prevailing approaches show a strong candidature for lithographic hotspot detection.

Optical Proximity Correction (OPC) is an important step in the optical lithography-based manufacturing process. Starting from 115 nm, lithography processes typically use OPC to resolve features acceptably. Advanced OPC technologies use model-based edge segment adjustments to achieve highly accurate corrections. The typical process for optical proximity correction suffers from a huge turn-around-time (TAT) and is well known to have time-consuming complexity especially at 40 nm and below. Therefore, in order to speed up process development and increase qualified pattern variations with good yield, we must find ways to speed up the OPC TAT. This paper presents a flow to construct layout hierarchy and increase OPC cell/template re-use to greatly reduce the OPC TAT using the Pegasus Computational Pattern Analytics (CPA) software.

Each day, semiconductor manufacturing companies (fabs) run distributed compute-intensive post-tape-out-flow runs (PTOF) jobs to apply various resolution enhancement technology (RET) techniques to incoming designs and convert these designs into photomask data that is ready for manufacturing. This process is performed on large compute clusters managed by a job scheduler. To minimize the compute cost of each PTOF job, various manual techniques are used to choose the best compute setup that produces the optimum hardware utilization and efficient runtime for that job. We introduce a machine learning (ML) solution that can provide CPU time prediction for these PTOF jobs, which can be used to provide compute cost estimations, provide recommendations for resources, and feed scheduling models. ML training is based on job-specific features extracted from production data, such as layout size, hierarchy, and operations, as well as meta-data like job type, technology node, and layer. The list of input features correlated to the prediction was evaluated, along with several ML techniques, across a wide variety of jobs. Integrating an ML-based CPU runtime prediction module into the production flow provides data that can be used to improve job priority decisions, raise runtime warnings due to hardware or other issues, and estimate compute cost for each job (which is especially useful in a cloud environment). Given the wide variation of expected runtimes for different types of jobs, replacing manual monitoring of jobs in tape-out operation with an integrated ML-based solution can improve both the productivity and efficiency of the PTOF process.

Multiple patterning lithography (MPL) is regarded as one of the most promising ways of overcoming the resolution limitations of conventional optical lithography due to the delay of next-generation lithography technology. As the feature size continues to decrease, layout decomposition for multiple patterning lithography (MPLD) technology is becoming increasingly crucial for improving the manufacturability in advanced nodes. The decomposition process refers to assigning the layout features to different mask layers according to the design rules and density requirements. When the number of masks k ≥ 3, the MPLD problems are N P-hard and thus may suffer from runtime overhead for practical designs. However, the number of layout patterns is increasing exponentially in industrial layouts, which hinders the runtime performance of MPLD models. In this research, we substitute the CPU’s dance link data structure with parallel GPU matrix operations to accelerate the solution for exact coverbased MPLD algorithms. Experimental results demonstrate that our system is capable of full-scale, lightningfast layout decomposition, which can achieve more than 10× speed-up without quality degradation compared to state-of-the-art layout decomposition methods.

Traditional modeling of computational lithography starts first by determining the functional relationship between the change in focus and the aerial image (AI) location of the optical model by setting constraints and then calibrating the resist model separately. In this process, built-in genetic algorithm (GA) tools usually participate in the parameter optimization process of only one model at a time. Additionally, GA tools are vulnerable to becoming trapped in a locally optimal solution. The practice of optimizing the optical and resist models separately may potentially miss better solutions. We propose a method to co-optimize the two models simultaneously. This is done by finding the Pareto optimal frontier of potentially better solution candidates that balance these two models. To avoid the local optimal solution trap, a method is proposed to increase the search range when the algorithm is confined. In the selecting and scoring models process, we quantify metrics that are typically made empirically by engineers to achieve higher levels of automation.

OPC is a key step to improve design fidelity when people transfer patterns from the photomask to the wafer. However, to complete a traditional OPC job in advanced technology node, a huge number of CPU cores and above several days are required. In this article, we proposed a pixel based OPC and deep learning OPC hybrid optimization framework. First, the pixOPC is done with the raw training clips. The pairs of the raw training clip and post OPC clip form the training data set. The training clip pairs are fed into GAN (Generative Adversarial Network) OPC architecture and the GAN network is trained. The GAN OPC generator is then validated to ensure that it has enough accuracy and does not overfit the data. The validated GAN OPC generator is then applied to generate OPC masks for the new design clips and the generated masks are refined with traditional OPC to exclude some unexpected outliers generated by the GAN method. We design the reversed high discretion pix2pix GAN to generate OPC masks. Its runtime and performance are compared with the model based OPC, pixOPC and U-Net. The generated OPC masks, simulated lithographic contours, EPE, PVBAND and NILS are compared. We find the GAN generative models have better performance compared with the traditional OPC, and the runtime are also much shorter.

Accurate prediction of Jacobian is essential for multi-variable optical proximity correction (OPC). The Jacobian means the small variation of edge placement error (EPE) induced by small mask bias of nearby segments under optical proximity effects. If the Jacobian can be accurately calculated, it is helpful for OPC iteration reduction, or EPE improvement for 2D shape mask patterns. Moreover, if this can be cost-effective, this approach can be easily extended to Full chip level. We changed expensive Jacobian matrix procedure into simple ML based Jacobian model inference. Thanks to efficiently chosen geometric and optical features and light ANN structure, our method can predict Jacobian 76% faster and 81% more accurate than intensity distribution function method. We also improved mask optimization algorithm by inserting small gradient iterations. Our mask optimization solver was 2 times faster than vanilla mask optimization solver. Through this effort, we constructed fast and accurate machine learning assisted mask optimization solver.

The Design Rule Manual (DRM) is a critical component in the introduction and release of new technology nodes. It is the reference manual of definitive requirements, documented in detail, on all information regarding design rules and technology node design requirements. The DRM is a contract between the foundry and the designer. Designs must meet all documented requirements to be accepted for manufacture. The DRM’s critical role in process design enablement obligates it to a very high quality standard. The DRM must be accurate, reliable, and clear of ambiguity. Qualification of the DRM is crucial as design rules become extremely complex with advancing technology. DRM teams must ensure all descriptions and figures are correct and clear versus target requirements from the beginning of the technology development stage. The qualification process should cover all typical cases as well as corner and unexpected cases. Traditional methods of targeted pattern creation leave gaps in ensuring a high quality DRM. Those methods often miss complex scenarios leading to incomplete DRM documentation or descriptions with vague ambiguity. Ambiguity in the DRM leads to improper DRC rule coding, resulting in erroneous DRC checking. This paper presents a synthetic pattern/layout generation approach to high quality and high coverage DRM and DRC qualification. The generated patterns flow into a post-generation-analysis-fix step that helps discover and analyze issues while initial design rules and DRC code is being developed. Guided random generation of legal layout patterns produces simple and complex pattern configurations to challenge the accuracy and consistency between the original intention of the complex design rules and DRC rule deck. The post-generation-analysis-fix step helps identify locations of potential discrepancy. Flushing out these discrepancies and ambiguities drives enhancements to converge on robust DRM documentation and consistency between design rule intent and DRC run set implementation from early development throughout the life cycle of process node deployment.

A yield prediction model with a corresponding cost of the ownership (CoO) and turn-around-time (TAT) analysis is studied on imec’s advanced technology nodes that include EUV and high NA EUV lithography. It also captures device variations from FinFET to CFET. Using modeled die-yield and the cost-of-ownership (CoO) for imec advanced technology nodes including N2, A14, A10, A7 to A5 technology nodes, we show there is a clear correlation trend in choosing a process technology. A precise methodology that can co-model the turn-around-time (TAT) which is inseparable in evaluating the manufacturability is also provided. As a conclusion, node-to-node scalability is proven to be a function of the manufacturability which will be represented to the yield, CoO and TAT metric, not just a function of the patterning complexity or photolithographic resolution that the industry is mainly chasing after.

Modern semiconductor fabrication pushes the limits of chemistry and physics while simultaneously employing largescale, cutting-edge processing techniques. While fab expansion and capital expenditures continue to grow, the human element has become ever more demanding and prone to error. To assist with this issue, computer-aided process engineering, process control, and tool monitoring will continue to rise in the coming years. In this paper, we present an APC-integrated, customizable solution to an in-fab processing segment. Through machine learning, we combine information from design-specific extracted features with processing and metrology data to predict oxide deposition thickness. The result is a design-aware augmentation for current metrology that can recommend accurate process recipe conditions for new layouts. We also present experimental results highlighting the benefits of adding design-aware features with in-fab data to anchor and support each other across layouts and technologies. This result paves the way to decouple, isolate, and quantify the individual influences each processing step imposes on different designs at various stages of the fabrication flow.

We propose a new model for active contours in inverse lithography based on a geometric partial differential equation. By cognitive analogy to the classic ‘snakes” model, the closed parametric contour of the interesting layout pattern is evolved under smoothness control, the influence of a distance-metric minimizing image force and an additional distance-regularized level-set (DRLS) pressure force. Numerical implementation is performed locally in the vicinity of zero levelsets with additive operator splitting (AOS) based semi-implicit differencing tenable for sufficient large stepsizes. Simulation results show that the computation efficiency is improved with reduced optimization dimensionality and the convergence efficiency is improved with sufficiently large stepsize when semi-implicit scheme is applied.

The backside of the silicon substrate is predicted to be heavily exploited by the next generation of integrated circuits to fulfill the increasingly challenging task of delivering current to billions of transistors. The buried power rail presented in this paper represents an enticing way to start transitioning from the frontside to the backside by moving the power rails in the silicon substrate. This is achieved by leveraging the large portions of Shallow Trench Isolation between fin-based devices. A metal layer is added to a conventional BEOL stack to enable this technology in commercial EDA tools for physical implementation and IR drop analysis. A comprehensive PPA evaluation of the buried power rail is performed at the block level, using a 64-bit CPU block and imec A14 nanosheet PDK. Typical physical design parameters are varied in the process to understand the impact of buried power rail in different conditions. The results show performance improvements both in iso-target (from 2% to 3.5%) and maximum frequency (from 9.5% to 12%). Both stem from a 7% shorter wirelength and 16% smaller area. From the IR drop perspective, better results are obtained with the buried rails showing a reduction up to 33% and enabling the use of sparser power delivery structures. This paper shows how moving the power rails to the substrate represents a powerful block-level knob for power delivery network optimization and as a performance booster.

Suboptimal layout geometries after optical proximity correction (OPC) might induce lithography hotspot, and result in degradation of wafer yield during integrated circuit (IC) manufacturing. Conventional hotspot correction methods have been widely conducted on post-OPC layout, such as rule-based or model-based hotspot fixing, but these methods might not completely solve hotspot issues due to the time-consuming process or model inaccuracy. Over the past of few years, the explosive growth of machine learning techniques has boosted the capability of computational lithography including hotspot detection and correction. In this paper, we focus on lithography hotspot correction with Generative Adversarial Network (GAN) to modify pattern shapes of hotspot and further improve lithographic printing of designed layout. The proposed approach first built a hotspot correction model based on different types of lithography rule check (LRC) hotspots, by training a pix2pix model to learn the correspondences between paired post-OPC layout image and after development inspection (ADI) contour image simulated from LRC tool. Then, we input hotspot-free contour image created from original hotspot into the deep learning model to generate supposedly hotspot-free mask image, and converted the mask image back into polygonal layout. Finally, mask layout with hotspot were partially replaced with predicted mask layout, and then examined with LRC simulation. Furthermore, we also implemented transfer learning for new hotspots captured from new design layout to expand the capability of our hotspot correction flow. Experimental results showed that this methodology successfully corrected lithography hotspots and significantly enhanced the efficiency of hotspot correction.

Process variation band (PVB) is important for a number of lithography applications such as yield estimation, hotspot detection, and so on. It is derived through multiple lithography simulations of a mask pattern while optical settings such as dose and focus are varied. Quick estimation of PVB has been studied. A simple approach assumes optical settings for innermost and outermost PVB contour; it requires only two simulations, but the assumption of such optical settings does not always hold. We postulate that two sets of good custom kernels exist; one set for lithography simulation to extract outermost PVB contour, and the other for innermost PVB contour. Since lithography simulation can be mapped to a convolutional neural network (CNN) with kernels corresponding to convolution filters, each set can be obtained by training corresponding CNN with a number of sample reference contours. Our experiments indicate that the average intersection over union (IoU) between reference- and predictedPVBs reaches 97% with 0 PBVs having IoU smaller than 50%. This can be compared to the state-of-art of PVB prediction using conditional generative adversarial networks (cGANs), where average IoU is only 89% with 12 PBVs having IoU smaller than 50%.

Due to insufficient lithographic margin, design rule based layout patterns can become killer defects on silicon such as necking and bridging. These may cause severe yield loss and progressive failure. This paper presents a weak pattern analysis methodology to improve process margin by eliminating risk factors at physical design level. We applied this method to the Back End of Line (BEOL) layers of 10nm class DRAM device. The concept of our algorithm is clustering similar patterns using Process Skew-Based Edge Tolerance (PSBET) of layout patterns. The clustered layout clips are analyzed through the After Development Inspection (ADI) contour simulation, and we design weak patterns on the Test Element Group (TEG) chip to check for actual defects. With our proposed method, we extracted layout clips from millions patterns of a full chip and categorized patterns of failure by 5 groups. Finally, we identified that the weak patterns detected by layout analysis methodology were 56% consistent with the defects detected on the wafer. We demonstrated that patterns with low process margin could be detected prior to mask tape-out. To prevent generation of weak patterns, we enhance layout design-rule coverage and build a hotspot library to gather data. This flow of pattern classification and hotspot detection is expected to be applied in sub-10nm DRAM and logic devices.

Reticle modification involving model-based optical proximity correction (MB-OPC) has driven generations of advanced CMOS nodes for more than two decades and may soon be carried over by inverse lithography technology (ILT). However, the demand for computational resources for ILT reticles cannot be addressed easily but only through massive parallel computation to this date. The development of quantum computing, in particular, quantum annealing algorism (QAA) is aimed to solve optimization problems in the real world, provided that the tasks can be framed into a binary quadratic model (BQM). Moreover, QAA is potentially capable of finding the global minimum solution of an optimization problem, instead of the local minimum provided by many gradient-based approaches. As the current ILT reticles have been largely generated using gradient-based algorithms, it is of great interest to investigate the applicability of QAA for reticle optimizations. We recast the mask optimization problem into a quadratic unconstrained binary optimization (QUBO) problem by defining the Hamiltonian as the difference between the target absolute amplitude image to that of an optimized mask. The approximation is valid due to the dominated first kernel in the sum of the coherent system (SOCS) approach for the aerial image calculation. The simulations are carried out in D-wave Advantage 6 system accessed through Amazon Bracket. Due to the limited number of qubits, we restrict the reticle optimization problems to N= 25, 36, 49, and 64 variables which map to a maximal 5760 physical qubits thru Pegasus embedding. In QAA, we investigate the effects of annealing time and inter-sample correlation, as well as the pausing strategies in the annealing schedule on the probability of finding the best solution to the target mask. We also compare the problem solved by QAA followed by the classical steepest descent (SD) algorithm versus the SD algorithm only. The hybrid QAA/SD approach produces the highest probability of finding the target mask with approximately two-thirds run time reduction from the SD solver only, suggesting that QAA indeed has the potential in finding the global-minimal solution.

Layout-to-wafer pattern fidelity in modern IC manufacturing has been guaranteed through model-based optical proximity correction (OPC), where the lithographic model calibration has relied on extensive gauge placements on edges or features with critical dimensions (CDs). The rapid development of deep learning neural network models has improved the accuracy of gauge-based models, thereby tightening the CD error budget for advanced CMOS nodes. Other applications of neural-network models also include the prediction of hot spots, etched CDs, sidewall profiles, etc. However, the rising applications of silicon photonics and curvilinear OPC can challenge the robustness of the guage-based lithographic model. In contrast, a calibrated lithographic contour simulator provides the flexibility to extract CDs at any location and allows the use of multiple OPC styles. Here we present a lithographic contour simulator based on Hopkin’s optical image formulation, followed by a photoresist model using Fully Convolutional Networks (FCN). The FCN resist model correlates the computed aerial image with the photoresist image extracted from scanning electron micrographs (SEM) with sufficient learning and inference, thus outperforming conventional neural network models. The FCN model achieves an average CD/CD = 1.69%, with the worst prediction coming from process variation. The lithographic contour simulator currently is implemented in i-line photolithography to successfully pattern large-area near-infrared (NIR) metalenses. The deep-learning neural network model is extendable to KrF and ArF photolithography through transfer learning.

Model-based optical proximity correction (MB-OPC) consists of fragmentation which is decomposed into segments and iterative simulations and corrections with a feedback system. Mask bias for each segment is iteratively corrected by heuristic rule-based PID control. Although mask pattern is various, the same PID parameters are adopted. We apply reinforcement learning (RL) as a PID parameters predictor. Pattern-aware adaptive PID control through RL has the benefit of EPE convergence. RL model receives layout features and PFT values as its inputs. The reward of RL model is designed for minimizing EPE from the current mask.

Mask three-dimensional (M3D) effects are non-negligible for imaging simulation of EUV lithography systems. Especially, the curvilinear mask obtained by inverse lithography technique (ILT) increases the difficulty to calculate the diffraction spectrum of the thick masks. In this paper, a fast thick-mask model based on multi-channel U-Net (MCU-Net) is proposed to solve this problem. The diffraction near-field (DNF) of thick mask in EUV lithography is characterized by four complex-valued diffraction matrices, the real parts and imagery parts of which can be represented by eight realvalued diffraction matrices in total. Then, all of the eight real-valued diffraction matrices can be synthesized together using the proposed MCU-Net model. The parameters of MCU-Net are trained in a supervised manner based on a precalculated DNF dataset of curvilinear thick masks. The comparison of the proposed method with some other learningbased thick-mask models is provided and discussed. It shows that the MCU-Net is efficient and accurate to simulation the M3D effect in EUV lithography.