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30 April 2023 A Synopsys TCAD-based workflow to support technology evaluation at 3nm and beyond
Robert Robison, Janet Wilson, Reinaldo Vega, Terence Hook, Frank Geelhaar, Jonathan Cobb, Tim Tsuei
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Proceedings Volume 12495, DTCO and Computational Patterning II; 1249510 (2023) https://doi.org/10.1117/12.2658572
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States
Abstract
Technology evaluation of new nodes is becoming increasingly complex; where transistor performance was once the critical metric, technology evaluation currently requires more complex metrics such as AC power and area. We present a method to utilize Synopsys TCAD to generate HSPICE collateral from device and process simulation to enable circuit simulation. This workflow is automated to support generation of packaged standard cell library collateral, enabling early analysis of more complex circuits which utilize automated routing tools to create. This workflow enables a much more accurate and complete picture of technology performance in a faster way than traditional PDK-based workflows.
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Robert Robison, Janet Wilson, Reinaldo Vega, Terence Hook, Frank Geelhaar, Jonathan Cobb, and Tim Tsuei "A Synopsys TCAD-based workflow to support technology evaluation at 3nm and beyond", Proc. SPIE 12495, DTCO and Computational Patterning II, 1249510 (30 April 2023); https://doi.org/10.1117/12.2658572
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KEYWORDS
Back end of line
Device simulation
Transistors
Multilayers
New and emerging technologies
Oscillators
Performance modeling
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