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1 June 1990 Automated inspection as part of a defect reduction program in an ASIC manufacturing environment
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Abstract
As critical dimensions on VLSI circuits are reduced below one micron, growing competitive pressures increase the importance of rapidly reducing and maintaining low defect levels. Conventional methods of analyzing process defects rely heavily on analysis of completed product and in-process particle monitors to control defect density and provide data to guide yield improvement efforts. Because the rate of yield improvement and the response to fluctuations in defect density are critically dependent upon the timeliness and accuracy of defect data, more advanced methods of in-process analysis must be used to detect and isolate process defects. Automated defect inspection, when used in conjunction with end-of-line failure analysis and other in-process defect monitors, provides a timely and accurate measure of process defects. An effective defect reduction program, utilizing automated inspection, includes efforts in both the control of process excursions and the reduction of baseline defect density. Control of yield limiting defects can be supported through the application of SPC techniques to monitor process defects and rapidly detect excursions in defect density when they occur. To identify the source of yield limiting defects and guide yield improvement efforts, inspection of wafers at sequential locations in the manufacturing process can be used to accurately and quantitatively locate the source of random defects. This paper describes the use of automated defect inspection, as part of a comprehensive yield improvement program, to facilitate both the detection of process excursions and the isolation of defects to a specific process step.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stan Strathman and Sue Lotz "Automated inspection as part of a defect reduction program in an ASIC manufacturing environment", Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); https://doi.org/10.1117/12.20047
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