1 June 1990 Optical method for the verification of integrated circuit and masking structures
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Abstract
The inadequacy of the stuck-at fault model has been well aired and documented.1 ,2All studies agree that this model does not reflect the physical failures of real devices,3 principally because such failures do not exhibit a 1 : 1 mapping onto the logic domain.2 ,4 Circuit layouts which are based on stick diagrams do however reflect the physical domain in sufficient detail to enable both structural defects, together with shorts and opens in metallic and non-metallic domains, to be detected and located. The author has proposed the adoption of a novel method which processes information obtained from a scanning laser beam reflected from a surface profile. Scanning may be of a raster nature over the surface, or follow a suitable path search along layouts. The latter search type has been simulated in PROLOG using breadth-first (BRFS), Euler (ES), and neighbourfirst (NFS) searches. It is suggested that by creating and modifying an acquired-knowledge database (AKDB), according to defect occurrence, it is also possible to search those regions where defects may be present in order of decreasing probability. Thus a useful library of the distribution of defect density statistics would be created by virtue of this proposal. The paper concludes that it is feasible to both detect and locate layout defects according to a prescribed range of defect size. The AKDB can be monitored to compile statistical knowledge of both uniformity of structure and defect occurrence, thus raising the yield figure and reducing cost. Such a topological approach to the testing problem offers a test structure for exploitation which is technology independent, relatively fast, adaptable to parallel processing, and may be interfaced with machine vision systems.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Robert Howard Jones, Robert Howard Jones, } "Optical method for the verification of integrated circuit and masking structures", Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); doi: 10.1117/12.20070; https://doi.org/10.1117/12.20070
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