Yield improvement of submicron devices using defect source analysis on AI interconnections

Toru Kobayashi; Yoshimi Shioya

doi:10.1117/12.20048

1 June 1990 Yield improvement of submicron devices using defect source analysis on AI interconnections

Toru Kobayashi, Yoshimi Shioya

Proceedings Volume 1261, Integrated Circuit Metrology, Inspection, and Process Control IV; (1990) https://doi.org/10.1117/12.20048
Event: Microlithography '90, 1990, San Jose, CA, United States

Abstract

Yield of submicron bipolar chip mounted on a supercomputer has been dramatically increased by the use of a 5-step experimental procedure. The procedure uses data provided from electrical test, automated defect inspection, SEM (Scanning Electron Microscope) and EPMA (Electron Prove Microscope Analysis) to characterize and eliminate killer defects. Yield improvement was quantified and compared to theoretical expectations. Introduction With higher packing density and bigger chip size, rapid yield enhancement becomes more critical.1 At the same time, defects impacting yield become more difficult to identify and eliminate. The most. difficult step in the yield improvement procedure is frequently the isolation of the defect source. More advanced methods of defect detection, data analysis, and compositional analysis are required to quickly eliminate killer defects in the submicron manufacturing environments of the 1 990's. Successful isolation of the source of killer defects, called defect source analysis, is a critical step leading to quick yield improvement. In this paper, a defect reduction procedure has been applied to a submicron bipolar device mounted on a supercomputer. The device has four aluminum interconnection layers, and a trilevel resist process is applied to the layer formations. A procedure is described using the following five step experimental design.

Citation Download Citation

Toru Kobayashi and Yoshimi Shioya "Yield improvement of submicron devices using defect source analysis on AI interconnections", Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); https://doi.org/10.1117/12.20048

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available