1 June 1990 Yield improvement of submicron devices using defect source analysis on AI interconnections
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Yield of submicron bipolar chip mounted on a supercomputer has been dramatically increased by the use of a 5-step experimental procedure. The procedure uses data provided from electrical test, automated defect inspection, SEM (Scanning Electron Microscope) and EPMA (Electron Prove Microscope Analysis) to characterize and eliminate killer defects. Yield improvement was quantified and compared to theoretical expectations. Introduction With higher packing density and bigger chip size, rapid yield enhancement becomes more critical.1 At the same time, defects impacting yield become more difficult to identify and eliminate. The most. difficult step in the yield improvement procedure is frequently the isolation of the defect source. More advanced methods of defect detection, data analysis, and compositional analysis are required to quickly eliminate killer defects in the submicron manufacturing environments of the 1 990's. Successful isolation of the source of killer defects, called defect source analysis, is a critical step leading to quick yield improvement. In this paper, a defect reduction procedure has been applied to a submicron bipolar device mounted on a supercomputer. The device has four aluminum interconnection layers, and a trilevel resist process is applied to the layer formations. A procedure is described using the following five step experimental design.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Toru Kobayashi, Yoshimi Shioya, "Yield improvement of submicron devices using defect source analysis on AI interconnections", Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); doi: 10.1117/12.20048; https://doi.org/10.1117/12.20048


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