1 June 1990 Evaluation of a silicon trench alignment target strategy
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An evaluation of an optical lithography alignment target strategy based on a trench structure dry etched in a silicon substrate prior to device fabrication is presented. Use of this silicon trench target provides a robust target which is necessary for alignment of difficult layers on processes employing multilevel metallizations with planarizing dielectric films. In comparison the use of other targets schemes are less effective on steppers that utilize a darkfield alignment technique when aligning these difficult backend metal process layers. Additional motivation for this study is the requirement of tighter overlay specifications at all levels as device geometries are reduced to the submicron region. This silicon trench target scheme minimizes the total root mean square overlay budget by aligning all process layers to the silicon trench target. Therefore this technique can effectively enhance efforts to scale device dimensions. In this study the effects of target polarity target dimensions target design and silicon etch depth of the target on process alignment latitude are shown for a submicron CMOS process of three layers of metallizations with intermetal planarizing dielectric films. The selection of thin films deposited over the silicon trench target during the process sequence was also optimized to enhance the silicon trench target. The process alignment latitude results of this evaluation are based on an assessment of alignment target signal integrity including signal to noise ratio and target symmetry. In addition quantification
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gary E. Flores, Warren W. Flack, "Evaluation of a silicon trench alignment target strategy", Proc. SPIE 1264, Optical/Laser Microlithography III, (1 June 1990); doi: 10.1117/12.20191; https://doi.org/10.1117/12.20191

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