This PDF file contains the front matter associated with SPIE Proceedings Volume 12751, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

Lasertec released the actinic patterned mask inspection (APMI) system ACTIS in 2019 and has since been providing it as an actinic inspection solution for EUV mask inspection. ACTIS performs high-resolution, high-throughput inspection of EUV photomasks. It detects all types of mask defects making lithographic impact because it uses the wavelength of light used in EUV lithography as its light source. While actinic inspection is typically known for its capability to detect phase defects, it is also indispensable for detecting phase shift defects on EUV PSM. ACTIS performs both die-to-die (D2D) and die-to-database (DDB) inspections and can inspect all types of EUV masks including multi-die masks and single-die masks. High-NA lithography is expected to be used for the EUV process at the technology nodes of N2 and beyond. The nextgeneration ACTIS has an objective mirror with a higher NA. This makes it possible to have different resolution characteristics in the X and Y directions, enabling it to meet the sensitivity required to detect defects in the anamorphic patterns used for high-NA EUV lithography. In addition, as design nodes become smaller, curvilinear masks will be adopted to improve resolution characteristics on wafers, which will require handling a large amount of design data per mask. For DDB inspection, which generates reference images using sophisticated, high-speed computer processing, the inspection of curvilinear masks is a major challenge. In DDB inspection, curve masks generate large amounts of data because complex curve shapes are approximated using polygons with a large number of vertices. It needs more computing resources and leads to a longer processing time. The reference images generated for inspection must be more intricate. APMI is necessary for pattern mask qualification of EUV masks with pellicles. However, the high sensitivity inspection of masks with EUV pellicles was prevented by the incident power limitation by heat load on the pellicle. Therefore, we have developed a new EUV light source that can minimize the thermal load. This paper describes the development results of the next-generation ACTIS for high-NA EUV lithography, the DDB inspection capability of ACTIS for curvilinear masks, as well as the requirements for APMI light sources, which differ from those of EUV scanner light sources, and the development result of Lasertec's EUV light source "URASHIMA".

Given the successful development in actinic pattern mask inspection (APMI), high-volume manufacturing of advanced chips including N5 and N3 was realized due to the defect-free masks provided by the TSMC mask shop. This achievement was attributed to the newly developed EUV source and GPU-based defect detection with machine learning (ML) assistance. Unlike conventional approaches which sustain less than two weeks, the rotated crucible fed by Sn fuel in the LPP (Laser-produced plasma) system provided one month of operating stability with ultra-low tin consumption. The newly developed LPP EUV light source has been moved towards double IR power to produce higher EUV photon counts, resulting in better throughput and inspection sensitivity. It enables captured images to possess an effective signalto-noise ratio (SNR) and reasonable inspection nuisance counts. The common technique challenges, Sn auto-refuel and debris mitigation, were overcome by auto-refuel and reuse, debris mitigation, and plasma position control. Moreover, the LPP system also showed its capability in performing pellicle inspection to prolong mask operation periods in wafer foundries. For the GPU-based inspection system, it provided the feasibility and flexibility in algorithm development compared to the FPGA approach. The TSMC developed machine-learning (ML) based rendering model played a key role in aligning features with tool images in D2D mode, as well as residue reduction of D2DB mode. All rendering models were implemented by CUDA coding and running on TSMC-customized GPU architecture to fulfill the goal of high-speed computation and defect capture rate that met production specifications. Combining with the ML model, proper detectors were designed for each specific feature, such as SRAF and curvy OPC design, and the performance of auto defect classification (ADC) with the model has been proven. By integrating all the work, it enabled the actinic tools to fulfill the requirement of massive production significantly.

Photomask contamination standards are used by leading-edge equipment suppliers to develop, qualify, and calibrate defect mask inspection and review systems. Mask shops at prominent device manufacturers also use mask standards to qualify inspection/review tools during process development and for periodic quality checks during manufacturing. Although perhaps widely overlooked, these standards are essential for a healthy mask ecosystem. Contamination standards are produced by depositing soft defects of known composition, size, and morphology at prescribed locations on a mask or pellicle surface (front side and/or back side). A typical standard consists of multiple circular spot deposits each with hundreds to thousands of uniformly dispersed particles. The electrophoretic deposition process is virtually indifferent to the substrate, having been applied to mask blanks, films (metal, nitride, resist, absorber), and patterned masks, both DUV and EUV. Challenges met over the past decade include sub-nanometer repeatability of nanoparticle size, deposition on mask edges (bevel and sidewall), deposition of large particles up to 20μm in diameter, and deposition on pellicles. Inspection of deposits on wafers are used as a proxy for inspection of masks and pellicles, enabled by repeatable deposition processing. Particle materials have evolved with inspection capabilities and challenges. Polystyrene latex (PSL) spheres, used ubiquitously as size standards for decades, have largely been replaced by SiO₂ spheres, which better withstand intense DUV and EUV energies. Recently, we have refined processes to deposit different defect materials such as alumina, silicon nitride, tin, and tungsten to emulate process-induced defects found in the real world.

Die-to-database inspection of optical patterned masks enables defect detection and subsequent repair for creation of defect-free masks regardless of single- or multi-die layout. The components required for optical die-to-database inspection include (1) optical photomask inspection tool with sufficient resolution to resolve the patterns of interest, (2) computational resources for (a) preparation of mask pattern data + (b) algorithms for detection and noise reduction to distinguish real defects from background variation, and (3) network and storage infrastructure to tie it all together. In this paper, we will present the first implementation of the die-to-database inspection flow on the MATRICS tool. To maximize tool utility, the system architecture decouples tool and compute resources, such that non-die-to-database inspections can proceed while die-to-database inspection also remains underway. Details of the mask pattern data preparation will be presented alongside real examples of detection capability from an Intel mask shop.

In prior work, the capability of novel nanomachining processes to repair TaN EUV absorber materials was shown using 1.8 aspect ratio (AR) AFM tips in line and space patterns down to 90 nm half-pitch. While these repair results were well within the requirements for EUV printability, they only demonstrated the capability to repair an absorber material which has become obsolete with the rapid development of EUVL technology. The introduction of boron into the absorber chemistry indicates a significant increase in the hardness of this material which can be a significant factor in tip deflection in nanomachining. In this work, test repair results are shown for an advanced EUV absorber stack containing a TaBN formulation. The repair dimensional accuracy and repeatability are analyzed along with the throughput and tip wear rates for this nanomachining process. The capability of the BitClean process to clean and finish these repairs will also be shown for this absorber type.

The rapidly increasing complexity of photomasks arising from free-form curvilinear mask shapes generated by Inverse Lithography Technology (ILT) has called for exploration of efficient and accurate native curvilinear data representation methodologies. The curvilinear Multigon extension to SEMI P39 OASIS format has been approved as a preliminary standard for the industry to evaluate Multigon-based post-tape-out data preparation flows. In this paper, we will present perspectives on opportunities, challenges, and applications of Multigon-based curvilinear data handling and representation. The representation of a closed curvilinear shape using multiple explicit or implicit Piecewise-Bèzier (PWB) curves will be described, including considerations for ensuring continuity of curves between neighboring Bèziers. A description of useful Multigon properties will be provided, which enables the development of operations fundamental to Computational Lithography, thereby enabling ‘native’ Multigon-based flows. PiecewiseBèzier to Piecewise-Linear (PWL) sampling methods (based on specified quantitative constraints) will be presented as an approach to convert PWB data to edge-based polygon representation such that PWB-based tools can be integrated and tested even in flows where certain components require operations on PWL data. Further, potential approaches, benefits and challenges related to development of Multigon-based data preparation flows will be discussed in the context of Optical Proximity Correction (OPC), Mask Process Correction (MPC) and multibeam mask writer data preparation. Finally, initial results on demonstrating curvilinear MRC (Mask-Rule-Check) on PWB data will be presented.

With the advent of curvilinear mask enabled by multi-beam mask writing and curvilinear ILT, full reticle curvilinear mask processing is emerging as one of the new challenges in electronic design automation and specially in the mask data preparation (MDP) domain. Whether for 193i or for EUV, curvilinear masks provide superior wafer results from larger process windows. Although the curvilinear photomask designs can provide an excellent opportunity to improve mask process window compared to traditional Manhattan designs, they put a strain on the MDP data path due to the increasing complexity of data representation. The mask industry is tackling this issue using a Bezier and B-spline based “Multigon” format to replace the traditional piecewise linear polygon-based formats. Pixel-based computing and consequently a representation of curves that is aware of the mask writer pixel size can further assuage the problems of data path and computational overhead in using curvilinear photomasks. This paper demonstrates the inherent advantages of pixel-based computing for curvilinear photomasks, when using a GPU-based platform, through comprehensive analysis and empirical evidence. GPU acceleration has played a very important role in making the full chip curvilinear mask correction for shapes represented using piecewise linear polygons. Since CPU-based algorithms perform better with piecewise linear polygons, this approach to GPU acceleration is necessary and important to the industry. By taking a different approach that assumes the presence of GPUs in a compute node, however, pixel-based computations are enabled, taking advantage of the Single Instruction Multiple Data (SIMD) nature of GPUs. This paper studies the advantages of using GPU acceleration for pixel-based computing in various mask processing and verification steps. The paper highlights the natural runtime predictability of pixel-based computing, which is in the order of number of pixels, or O(p), irrespective of the complexity of the mask shapes. The paper also emphasizes that pixel dose equivalence and information theory provide a mathematical basis for the practical accuracy of pixel-based approach towards MDP. Pixel-based computing has been the backbone of various fields in computer science and computer-aided design (CAD) tools. However, it is still a relatively unexplored computational paradigm for the photomask industry, especially in the mask verification and processing steps. GPU performance scales by bit-width rather than by clock speed. The continued scaling of GPU processing speed has enabled the shift in perspective towards GPU-based computing. This paper concludes that the O(p) approach for GPU acceleration enables accurate and practical data processing for curvy masks governed by information theory, as we leap into an increasingly complex curvy world.

In recent years, Curvilinear Mask technology has emerged as a next-generation resolution enhancement method for photomasks, providing optimal margins by maximizing the degree of freedom in pattern design. However, this technology presents challenges in defining layout design rule limit based solely on geometric information rules based solely on geometric information such as width, space, and corner-to-corner. With the introduction of Multi Beam Mask Writers for Curvilinear pattern production, brand-new violations of Mask Rule Check(MRC) have occurred, which cannot be explained by geometry terms alone. In this study we propose a deep learning-based method for detecting MRC violations using the state-of-the-art Transformer architecture, drawing an analogy between the vertices of curvilinear patterns and words in natural language. The proposed MRC binary classifier demonstrates improved performance compared to traditional rule-based MRC and CNN-based MRC methods. Importantly, our method exhibits robustness in recall, ensuring that defective patterns are not misclassified as normal, preventing missed defects. Moreover, by employing attention maps to visualize deep learning results, we gain explainability and reveal that MRC violations may arise from issues related to the fabrication of specific designs, rather than being solely attributable to geometric features. This insight contributes to a better understanding of the challenges associated with Curvilinear Mask technology and offers an effective solution for detecting MRC violations.

With the advent of advanced nodes, curvilinear mask processing is becoming the convention. Adopting complex curvilinear shapes for modern photomasks using ILT (Inverse Lithography Technique) may aid the pattern fidelity of complex designs. The curvilinear working group has convened on the addition of the MULTIGON record to the OASIS format. MULTIGON is accepted as a preliminary standard in OASIS format for the exploration of new flows and their advantages. Multibeam mask writers are becoming the standard solution at advanced nodes due to their constant write time and ability to pattern complex designs. Multibeam fracture will be pivotal in the MULTIGON based data preparation flows. In this paper, we demonstrate the readiness of Calibre multibeam fracture tools to accept MULTIGON input and generate fractured data to machine format. Existing multibeam mask writers expect Piecewise-Linear (PWL) data as input to their data path. This paper explores two different quantitative methodologies for conversion of MULTIGON input in fracture to Piecewise-Linear output, enabled by the Calibre Mask Data Preparation tools supporting multibeam fracturing. We investigate the impact of these two methodologies: edge-length based and deviation-tolerance based, while processing MULTIGON inputs, and their impact on mask contour quality. We also analyze the impact of the different sampling methods and their sampling values on the mask contour using a nominal EUV mask process model and present results related to these experiments. Consequently, we aim to deduce the acceptable sampling methods and their limits while respecting the sampling frequency described by the mask data preparation process.

With the introduction of the multi-beam mask writing (MBMW) technology, efficient processing and precise patterning of curvilinear mask shapes are becoming increasingly important due to the wafer lithography advantages associated with the shapes. However, as the complexity of the curvilinear mask shapes increases, it becomes difficult to precisely characterize the curvilinear mask shapes. Barrier to this is prediction and reflection of the nature of curvilinear mask shapes. Therefore, in the industry, a novel algorithm method for accurate patterning is a major concern. In this study, we discuss the status of curvilinear mask shapes and patterning technology. By adopting machine learning, we develop a novel algorithm with considering the nature of curvilinear mask shapes. To evaluate practical use and accuracy of model, we demonstrate that the algorithm has significant value to guarantee the mask critical dimension (CD).

Displacement Talbot Lithography (DTL) is an emerging photolithography technique for printing high-resolution periodic patterns. The image recorded through the DTL process differs from those created in projection printing or contact/proximity techniques, not only because it uses all longitudinal axis image planes, but also in the way the object (mask) transmission function is transformed into the recorded image. We present the main parameters involved in modeling the DTL patterning process and give examples relevant to applications such as AR/VR waveguide production. We also compare DTL to simulated projection lithography implementations. Like the well-known projection lithography case, the ability to accurately model and predict printing results is essential to exploring the process limits and possibilities with this new exposure technique.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present the most recent results for cross matched machine overlay and single machine overlay. For defectivity, we review random defect generation and particle adders. We then move on to discuss the technologies being introduced to establish a robust ecosystem for NIL. Topics include pattern transfer, simulation and data analytics designed to shorten cycles of learning. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Lasertec develops and manufactures inspection and measurement systems that meet the requirements of EUV lithography. Lasertec has successfully developed an actinic blank inspection (ABI) tool and released ABICS E120, a EUV mask blank inspection and review system that contributes to defect management and yield improvement in the production of EUV mask blanks. With the introduction of high-NA EUV scanners and the further progress of process nodes, actinic inspection tools will need to detect even smaller defects. Lasertec is developing a next-generation ABICS for such advanced nodes, eyeing its release in 2024. Its target performance is a sensitivity to detect defects 1nm high and 30nm wide with a coordinate accuracy of 10nm.

EUV photomask blanks are coated with an ion-beam-deposited (IBD) multilayer mirror of Mo/Si,. IBD is further a candidate for pellicle processes, due to its low defect density and uniform coating. The within-mask uniformity requirement is currently +/- 0.015nm in Central Wavelength (CWL) across the 6” x 6” area., requiring film uniformity of ~ 0.1%. To avoid stitching under high-NA anamorphic projection, larger form-factor masks and pellicles are being considered. Proposals include 300mm round or 12” x 6” rectangular blanks. We present simulations and data for the uniformity performance of the Veeco ion beam deposition tool over the double-sized active area, namely a rectangle of 104 mm x 264 mm. We demonstrate that the non-uniformity of today’s processes-of-record could result in 3.3x higher nonuniformity over the extended area, implying a CWL uniformity of +/- 0.05 nm. We then demonstrate process and hardware modifications to enable CWL uniformity recovery to better than +/- 0.015 nm.

EUV Mask for High Volume Manufacturing of semiconductor device have already became accomplished facts. Therefore, developing a flexible and controllable process capability for various film stack EUV blank structure and production is crucial. The requirements of high compatible process window need to sustain 1-nm critical dimensions (CD) control and etch stop on capping layer with zero damage. For conventional EUV blank, dual layer TaN substrate is proposed as state-of-the-art EUV photomask blank absorber material being comprehensively evaluated. Film stack material needs to be co-optimized with developing and etching process to keep pattern profile/fidelity, capping layer quality and durability, and defect density. Hence first of all, the novel etching strategy for mitigating capping layer damage to have better Ru durability improvement will be reported. Secondly, the developing process optimization to lower the defect counts caused by wettability change due to various absorber material will show. Finally, the pattern fidelity change caused by various etching selectivity between hard mask and absorber will be discussed in this paper.

Merchant photomask companies service the majority of the 14nm and greater nodes globally. These industry important nodes are facing mask supply challenges in the coming decade due to new organic growth and tool obsolescence. The first factor driving photomask volume is the significant wafer capacity being added globally at mid and mature technologies (>=28nm). The semiconductor growth is being driven by macro market trends including a renewed global appreciation of the strategic nature of the semiconductor business. The growth also is the result of new technology innovations like automotive electrification & ADAS, Artificial Intelligence, telecom (5G/6G), IoT, green power, and medical applications. The overall semiconductor business is forecasted to grow upwards of 8% CAGR from 2022 – 2030 1 with a significant portion occurring in Mid and Mature Technologies. This growth will require significant non-leading edge mask capacity. This paper will quantify the growth and the availability of tooling. Historically, photomask equipment makers produced new tools for the “leading edge” and the trailing nodes were serviced by previous generations of advanced photomasks tools. Fortunately, the photomask equipment manufacturers responded to the trailing edge needs and have introduced tools and upgrades to begin addressing this market. The second issue facing the photomask industry is significant equipment obsolescence for the mask tools that support mature technologies. This paper quantifies the obsolescence challenge. The dual factors of new organic growth and tool retirements has created a shortage of mask supply at the mid and mature nodes. There are challenges to add mask capacity to these mature nodes in an economically viable fashion. We believe that cooperation between mask maker, tool suppliers and mask customers is crucial to ensure that the predicted semiconductor growth does not face the risk of being constrained by photomasks.

Advances in technologies such as 5G, internet of things (IoT), automotive and medical devices, to name a few, have created a new demand for mature node IC devices. This, in turn, has accelerated the introduction of new mature node designs and raised the demand for photomasks serving these products. Manufacturing mature design node ICs and photomasks requires high volume, high yield, quick turn and price sensitive processes. For example, laser writers can be the preferred photomask patterning solution for those applications as they are fast and cost efficient compared to ebeam writers. In order to address the market and the expanding design variety (e.g., curvilinear shapes, AI generated designs, chiplets) of mature node applications, we have developed a suite of capabilities leveraging advanced data modeling that helps deliver efficient and reliable production of mature node photomasks. Examples include inter-tool and inter-site process matching to scale mature production and address tool end of life challenges. Adapting novel design styles to higher productivity, cost effective platforms such as laser writing is also an area of emphasis. We present various cases where our model driven data techniques have impacted mature node productivity and resiliency by addressing the increasing unit demand and design complexity. In addition, we highlight elements of characterization, model building and deployment within these mature node data solutions.

Since several years, there has been continuous focus on legacy tools for mask making and the critical requirements to address the end of life of equipment which has been workhorse for volume production. Toppan Photomask Company, Ltd. (TPC) has presented several papers on this subject and brought this to attention to many equipment manufacturers and other mask shops who have also shown keen interest to support the manufacturers who are willing to take up this task to provide solutions. HTL Co. Japan Ltd. And V Technology Japan has teamed up to manufacture equipment for the semiconductor mask making legacy tools and one such example is successfully manufacturing the mask repair system with support from TPC. Mask inspection, Registration, FIB repair and others also being addressed, and one attractive feature is to give an opportunity to enhance the performance of these new replacement tools by using AI software for defect classification for the system. We will discus our development process and capabilities served for legacy tool replacement.

Photonics applications generate more and more interest and they are on the way from research to commercially available products. However, due to versatility and the currently related manufacturing volume of the potential applications, efficient patterning techniques are required. Vistec’s electron-beam lithography systems with Variable Shaped Beam (VSB) and Cell Projection (CP) provide a flexible solution to generate these kind of photonics structures even on large areas. In case of arbitrary curved structures intelligent data preparation software solutions as JES-approximation and target contour calculation can be applied. An example is given to demonstrate the feasibility of these approaches specifically on cell projection.

Since the introduction of EUV, ASML and its industry partners have continuously improved the reticle defectivity levels in the volume manufacturing flows. In this paper we will show the progress over the years in reticle defectivity performance and what was done to achieve this. Next, an outlook of the defectivity improvements of the next product, NXE:3800 will be given. Finally, on the longer term, it will be shown how defectivity mitigation will be developed in the future platforms. In detail, these future developments extend the defect mitigations from the current cleanliness and flow optimizations further into the electrostatic realm. An overview will be given of the improvements planned in the EUV scanner, and the necessary changes needed on the EUV reticle infrastructure to fully benefit from these improvements. With all changes implemented it will be shown that electrostatic particle control can achieve a reticle defectivity reduction by more than 50%.

As extreme ultraviolet lithography (EUVL) technology progresses to support more advanced nodes, mask designs are becoming more complex and difficult for mask makers to produce with the required fidelity. Resolution enhancement techniques (RETs) including mask optical proximity correction (OPC) models and the addition of sub-resolution assist features (SRAFs) are now critical technology enablers. Early adopters of EUVL benefited from the resolution improvement provided by the shorter wavelength. To extend the benefits of EUV to smaller technologies and broader applications, SRAFs are valuable tools to maximize the process window for a variety of critical layers which require both bright and dark field imaging. Regardless of mask tone, because of the short wavelength of EUV radiation, very small SRAFs are required, thus patterning SRAFs for EUVL poses significant mask process challenges. E beam exposure and resist characteristics are key factors for important patterning attributes including minimum resolvable size, line edge roughness (LER), corner rounding (CR), and line end shortening (LES). Patterning dark SRAFs for bright field masks involves an additional challenge of overcoming mechanical forces on these small structures that can cause feature toppling or collapse. In this study, we demonstrate a mask process capable of patterning dark SRAFs on mask at line widths below 25nm (4X). We will discuss patterning solutions including innovations in both the physical mask manufacturing processes as well as mask data preparation techniques, such as mask process correction (MPC). We will utilize advanced characterization techniques to evaluate SRAF pattern fidelity on the mask and its predicted impact on wafer printing performance. A process capable of resolving sufficiently small SRAFs enables an on-wafer analysis to validate whether the predicted lithographic benefits can be demonstrated. Finally, we will review the outlook of continued shrinking mask resolution requirements from both a design value and process implementation perspective. The coming challenges for EUV mask makers include supporting not only ever increasing design complexity, but also the introduction of new mask materials, including phase shift masks (PSMs) as part of the overall RET solution.

The high numerical aperture EUV exposure systems aim to target a 16-nm pitch to extend Moore's law throughout the next decade. However, thinner photoresist layers and worsened stochastic effects due to photons hitting the wafer at a shallower angle is a major concern. Furthermore, the projection optics utilize an anisotropic reduction factor, which remains an open issue, requiring a dual "half-field" mask exposure sequence or a 12-inch mask for each high-NA EUV layer. Therefore, the use of attenuated phase-shift masks (APSM) to extend 0.33NA to a 28-nm pitch becomes relevant. We will discuss the prospects on optical properties refractive index (n,k) optimization with material selection, feasibility of achieving a 28-nm pitch, 3D effect mitigation and the impact of mask tonality (dark tone vs clear tone). Finally, the challenges on the needs of new APSM materials that meet the requirements of high temp thermal stability, durability under mask clean solution, its dry etching characteristics, the corresponding repair process will be addressed and the experimental results on the Ru-based candidates will be shown.

With EUV Attenuated Phase Shift Masks (aPSMs) rapidly approaching maturity, actinic metrology soon will be required to ensure phase accuracy, uniformity, and stability. The target phase shift is carefully designed to an optimized value, which is not 𝜋, but typically around 1.2𝜋 for optimal printing at critical feature sizes. The additional 0.2𝜋 phase shift is necessary due to mask 3D effects (M3D), which increasingly distort the nearfield scattering and phase as the feature size is reduced. Therefore, EUV attenuated phase shift masks require metrology, not only for the relative Fresnel phase shift between large-area multilayer and absorber regions, but also for the feature-dependent pattern phase shift in the near-field scattering. We demonstrate a metrology solution for measuring the in-pattern phase shift using spectroscopic variable angle scatterometry. The measurements are performed using the commercially available EUV Tech ENK (EUV n/k tool), based on a compact continuously tunable laser-produced plasma light source. In this presentation we describe experiments validating the accuracy and precision of actinic scatterometry-based pattern phase measurements conducted on the ENK platform on seven samples of EUV attenuated phase shift absorbers of varying thickness. We demonstrate good agreement with simulation on measurements of phase vs absorber thickness and phase vs grating pitch, validating the suitability of this measurement for measuring the actinic phase shift of an EUV mask.

The EUV reticle masking process has enabled the creation of smaller and more intricate integrated circuits, which are essential components of modern electronic devices. However, ensuring defect-free control and evaluation in the cutting-edge EUV reticle masking process is a challenging task. Currently, every potential defect must be judged by wafer printing assessment for almost 3 days, which can be both time-consuming and expensive, and even commercial approaches are incapable of meeting the demands of high-volume manufacturing. In this paper, we successfully developed the EUV Actinic Mask Review System (AMRS) to emulate wafer printability behaviors, utilizing a stable LPP EUV source with over 95% available time and a specialized TSMC-made SMO to achieve high throughput for more than 80 sites/hr. In addition, various EUV resist models have been developed to emulate the risk defect printing assessment with good matching results, and an in-house automation EUV defect analysis platform was developed to achieve fast and accurate areal image measurement. With this solution, all EUV repaired and potential defects, including 18nm HP L/S, ML defects, and even through EUV pellicle defects, can be addressed in technology nodes N5, N3, and beyond N3, on the brand-new actinic review platform. The development of the EUV Actinic Mask Review System represents a significant advancement in ensuring the quality and reliability of semiconductor devices. It provides a practical solution to the challenges posed by the EUV reticle masking process and enables the production of defect-free integrated circuits, paving the way for the continued innovation and progress of the semiconductor industry.

Extreme ultraviolet (EUV) mask metrology and inspection is crucial to evaluate the quality of devices realized by EUV lithography and to obtain the required yield. Actinic (i.e., at wavelength λ = 13.5 nm) mask inspection is particularly essential, as this wavelength ensures an imaging resolution and overall imaging physics that matches the operative condition of the lithography scanner. In recent years, various groups have explored coherent diffractive imaging (CDI), and particularly ptychography, as a candidate method for actinic EUV mask inspection. The simplicity of the ptychography approach, the absence of expensive lenses, and the possibility to image both amplitude and phase structures make this method particularly appealing. Despite these advantages, ptychography suffers from throughput limitations dictated by both the long data acquisition process and the time–demanding phase retrieval step. While the former challenge can be mitigated by advancements on source brilliance and detector technology, the latter clearly demands improvements on the algorithmic front. In this paper, we present our recent results on the study of deep learning as a means to achieve fast, high quality, and phase-sensitive reconstruction of aerial images of EUV masks, given the acquired data and the abundant a–priori information on the geometrical layout and chemical composition of the samples. We show that, once trained, the selected Deep Neural Network (DNN) architecture achieves a much faster reconstruction of the sample compared to the standard ptychography approach, while retaining high quality in both magnitude and phase images of the object.

Anamorphic High-Numerical Aperture (NA) EUV photomask manufacturing presents some unique challenges and opportunities in Critical dimension (CD) Scanning electron microscope (SEM) metrology. Novel methods of beam scanning condition are needed to improve image resolution and reduce image blurring to enable reliable metrology for the curvilinear mask era. Additionally, electron optics stigmation monitoring plays a major role in ensuring the horizontal to vertical (X-Y) CD Average to target (ATT) tool matching is not drifting due to aberrations, which are key for anamorphic EUV mask metrology. In this paper, we show the correlation between offsets in Condenser lens, Aperture balance, and electron beam Stigmation offset and its impact on horizontal and vertical feature CD ATT and CD uniformity measurements. Using Advantest E36xx Scanning electron microscopes we also present preliminary results, from improving measurement repeatability (ATT and CDU) on different mask substrates by incorporating Shadow reduction scanning (SRS), enhanced charge suppression using Charge neutralization technology and modulating dose of the beam (which is a function of scan condition and beam condition) In conclusion, we summarize the key metrology advances needed for next generation CD-SEM tools for High NA EUV photomask metrology, such as automated column optics monitoring, shadow reduction scan, design-based site focusing, high degree of measurement precision better than 0.5 nm, charge mitigation capabilities, high Throughput (TPT), enhanced stage performance accuracy, among others.

In the semiconductor industry, photomask quality depends on various aspects including critical dimension (CD), overlay to other layers, defects, etc. Conventionally, photomask metrology tasks are performed by separate tools. For example, KLA LMS IPRO is used for registration, while CD-SEM or optical microscope is used for CD measurements. However, current CD tools have time-consuming measurements and difficulties to providing spatial CD variation across the photomask. To address these challenges, LMS IPRO tool, originally designed for registration measurement, provides a portable and fast CD measurement solution. The feasibility of CD measurement on LMS IPRO comes from its image processing mechanism. Algorithms analyze the intensity of captured images to figure out the pattern edges. The calculated CD commonly has deviation to the actual CD due to the unknown edge intensity threshold. Thus, we fed LMS IPRO the actual CD to do calibration before using this function in production scenarios. The calibrated CD ranges from 0.5μm to 13μm, which covers the mature technology node product sizes at Quanyi Mask Optoelectronic Technology Co. Ltd (QYMask). Verification results proved that LMS IPRO meets QY Mask’s mature-node mask CD measurement specifications. Therefore, it could (a) be temporary substitution in case optical CD tool is down, (b) concurrently measure CD and registration, (c) provide fast pre-check of CD uniformity.

Curvilinear OPC has been developed for improved process window, more freedom in mask constraint and better MRC enforcement. Combined Curve OPC with ILT can further improve mask synthesis flow. We demonstrate hybrid curve OPC/ILT flows for more flexible deployment. High NA OPC together with anamorphic MRC can be well handled in this platform. Curve OPC can be deployed in co-optimization flow like litho-etch OPC, process window aware OPC, etc. Correction of any angle layout is challenging. We present our OPC solutions in handle of any angle layout and demonstrate good correction results.

Curvilinear mask is getting more widely used as a key technique for resolution enhancement with the progress of feature size shrinkage and multi-beam mask writers (MBMW) adoption. However, it is challenging to print curvilinear pattern accurately, which makes mask process correction (MPC) indispensable for curvilinear mask data preparation. It is known that pattern fidelity degrades at high curvature region by process blur. This degradation leads to various issues such as curvature loss and poor CD quality on printed curvilinear masks. Furthermore, due to anamorphic lithography systems, high-NA mask data is likely to contain patterns with higher curvatures compared to 0.33NA mask. Therefore, improving the accuracy of MPC on high curvature region is becoming more important. In this paper, we present a novel MPC method which deforms shape of high curvature region of any curvilinear pattern aggressively to achieve good fidelity. Using simulation and printed results of ellipse patterns with various curvatures, we will show that this MPC technique can improve pattern fidelity in regions of high curvature.

Extreme Ultraviolet (EUV) mask has Critical Dimension (CD) errors from various kinds of sources. Those errors are controlled for and corrected by proper correction methods such as fogging effect correction (FEC), loading effect correction (LEC), proximity effect correction (PEC), mask process correction (MPC) and so on. The corrections are mostly done independently. For example, conventionally CD nonlinearity has been the scope of mask process correction (MPC) and proximity effect has been that of proximity effect correction (PEC) because the interaction range considered is different from each other. But in order to improve the CD quality, we may need to consider the residual errors of PEC in MPC as well. For this purpose, we evaluated a new MPC method, named PEC-aware MPC, which considers writer's internal PEC for both model optimization and correction.

In this paper, we present our innovative work of using Siemens EDA Calibre® Machine Learning (ML) assisted Optical and Process Correction (OPC) verification tool to effectively capture all kinds of hotspots using one single constraint across the whole layout for each failing mechanism, for example one constraint for bridging failing mechanism, one constraint for pinching failing mechanism, etc. The pattern differentiation is accomplished by ML classifier. The output data volume is controlled by using classification limiting function instead of tuned constraints. This work significantly improves the effectiveness of capturing and not missing real hotspots yet simplifies the OPC verification recipe setup and engineering workload. The unique hotspots count on full chip using this new strategy can be at thousand level. This makes the Machine Learning assisted hotspot capture new strategy practical to prepare hotspot monitoring points for wafer verification, for example SEM inspection.

The multi-beam mask writer MBM-3000 is launched in 2023 for next generation EUV mask production. It is equipped with 12-nm beamlets and a powerful cathode that brings out a beam current density of 3.6 A/cm², in order to achieve higher resolution and faster writing speed than our current writer MBM-2000PLUS. New optics with a next-generation blanking aperture array (BAA) is installed in order to double the beam count. The optics is designed to reduce the Coulomb interaction effects. It is equipped with aberration correctors to reduce image field distortion and other types of aberrations to obtain the best beam performance. Patterning resolution is improved by these measures. Writing tests confirmed that the MBM-3000, which uses a 1.5X larger beam current than the MBM-2000, simultaneously enhances both resolution and throughput.

Critical Dimension Uniformity (CDU) of photomasks written with 50 kV e-beam writers is very sensitive to scattering and mask process effects such as etch loading. The interaction distances of those effects vary by about 6 orders of magnitude and range from around 10 nm to around 10 mm. With the introduction of 50 kV e-beam writers, tool manufacturers also developed methods for compensating the most significant scattering effects, namely backscattering, often called PEC for Proximity Effect Correction and fogging (also called FEC for Fogging Effect Correction). E-beam writers, including the most advanced multi-beam writers, use local dose modulation of the exposure dose as described in [1]-[3] to compensate for those longer-range scattering effects. This method works reasonably well for older technology nodes but starts to be a limiting factor for most advanced EUV masks which have to meet very high CDU specifications. The reason is that the Critical Dimension (CD) response to dose is not constant across different mask shapes. For example, very small features like sub-resolution assist features (SRAFs) have a higher ΔCD/ΔDose response than larger features, since smaller features have a more gradual image edge slope. So far it has not been reported in the literature that Mask Process Correction (MPC) applications take the e-beam writer corrections into account when correcting for shorter-range non-linearity effects. Ref. [4] describes an attempt to combine forward and backscatter compensation as an off-tool MPC application where all corrections seem to be achieved via dose modulation. This paper describes a method for integrating the e-beam writer dose modulation into the MPC engine, so that the actual exposure dose at any given location on the mask is taken into account when applying shape based, short-range MPC. With this extension of MPC, a fully consistent short- and long-range correction is possible, even when the actual long-range corrections are applied on the e-beam writer and not directly during the offline MPC step.

Reticle defect problem caused by different reasons is an unavoidable issue for mask application in fab, which has great influence on the quality and yield of chip product. With the development of chip pitch size, defect management became increasingly important for the higher demand of defect printability. For different patterns of reticle, the impact is quite different owing to the defect location relative to patterns is different which may impact critical dimension (CD) and actual pattern distort on wafer and result in product yield loss. In this study, we used a special algorithm to combine die to die detection results with MEBES data, and defined the defects risk with the energy attenuation (energy loss) of the whole pattern region which different from traditional point-to-point comparison in KLA inspection equipment. Besides, we introduced sensitivity factor(S) for better evaluate the defect risk. The mathematical relationship between the size of the mask defect and the wafer CD are verified by experiments and based on the experimental results, we established the energy loss auto measurement system for monitoring and analysis system of the defect of the hole pattern mask by correlate the size of the defects to the light energy loss rate, which effectively reduces the process risk caused by the mask defect.

CD-SEM is widely used to determine photomask CD performance, SEM image accuracy is crucial for CD measurement. SEM image blurring caused by charging on a type of binary photomask is a major issue we encounter during manufacturing, not only the image form is not clear on Isolated Clear patterns, also obvious CD deviation is observed on Isolated Dark patterns. We investigate into this issue and search for methods to remove residual charge on photomask. We found that these residual charge cannot be removed by electrolyte solutions in cleaning process but will disappear after a few days in fabrication environment. Furthermore, we found these phenomena reappear after UV radiation in close distance or O₂ plasma sputtering on the photomask. In this research, we prove that sputtering a mixture gases plasma can effectively eliminate this phenomenon without any negative impact on the binary photomask itself.

Digital lithography shortens development cycle time. Laser-based lithography is slow and lacks in overlay precision. The DIGITHO programmable photomask fits into standard photolithography steppers without system modifications. It can generate a different mask for each exposure. DIGITHO offers the most cost-effective solution for die-level serialization and fast prototyping to high throughput manufacturing.

In Dynamic Random Access Memory (DRAM) manufacturing process, contact hole (CH) patterns are critical and challenging array layers. Compared to line/space patterns, CH patterns generally tend to have a higher Mask Error Enhancement Factor (MEEF), therefore it will bring big challenges to wafer Global Critical Dimension Uniformity (GCDU) control, and it is also obvious to observe that the intra-field CDU error contributes mainly to the wafer GCDU variations compared with inter-field error. To improve CH patterns’ intra-field CDU, lithography process generally uses ASML scanner dose mapper (DOMA) solution. Here we introduce a new intra-field CDU improvement technology called CD Correction (CDC) by mask tuning, which is developed by Carl Zeiss and can obtain local illumination transmittance control with higher space resolution than DOMA. In our CDC application cases of contact hole (aka 2D pattern) layers, CDU in both X-Y directions is crucial for process, but different improvement results are found. When CDU in one direction is fully improved by CDC, improvement in the other direction is often insufficient or excessive and hard to achieve a win-win effect. By further experiments and analysis, the key factor we figure out is CDCR (CDC ratio), which is different in X-Y directions. In our work, first, we present a CDC implementation approach that trades off both X-Y directions of improvement. Second, the principle of different CDCR in X-Y directions is explored, it provides a theoretical interpretation for different CDCR and can predict CDCR in future applications.

The technology node shrinks years after years. To guarantee the functionality and yield of IC production, the resolution enhancement technology becomes more and more important. Both optical proximity correction and inverse lithography technique need a precisely calibrated lithographic model. A mask of test patterns needs to be prepared and the lithographic experiment has to be done with it to obtain the CD SEM data for the model fitting. It is beneficial to select the test pattern efficiently. Fewer number of test patterns should be selected without compromising their coverage capability and the accuracy of the lithographic model. We present a machine learning method based on the convolutional autoencoder and core set selection method to achieve above goal. We optimize the existing test pattern mask by selecting parts of gauges out. The OPC models calibrated with the selected data are compared with the models calibrated with original test patterns to evaluate our method.

The contour data extracted from SEM wafer images after the lithography are widely used in the critical dimension (CD), edge placement error (EPE) measurement. It is important to obtain the contours fast and accurate before the analysis of lithographic process and calibration of the lithographic models. Without the accurate contour data, the complete CDU, PVband analysis and inverse lithography technique are hard to realize. With the continuous shrink of the technology nodes, the demand for the accurate contour extraction increases. However, fast and accurate contour extraction from SEM images with defects and noises is challenging. We apply the U-Net to the semantic segmentation of SEM images. The contour extraction and evaluation can be done better after the image segmentation. Our experimental results show that satisfactory contour data of various types of lithographic patterns can be obtained with noisy SEM images.

Mask corner rounding refers to the unintentional rounding deviation of sharp corners or edges during the mask making process, that is caused by the inherent limitations of the e-beam exposure system, such as beam blur, proximity effects, and the resist exposure process. It can have significant consequences on the lithography of chip manufacturing. This article compares the mask corner rounding behavior under different electron beam sizes and presents a novel Optical Proximity Correction (OPC) approach that incorporates mask corner rounding for various dimensional rectangular shapes, named Rounded Corner Aware OPC (RC-OPC). Contrasting with traditional OPC that rely on a single value for simulating mask corner rounding, this innovative OPC approach delivers substantial advantages including increased accuracy, exceptional lithographic performance, and better pattern fidelity, leading to a more dependable and robust process.

With the full-scale adoption of EUV exposure tools, the use of Metrology and Inspection systems adapted for EUV process evaluation is increasing. In particular, with the increased durability of Pellicle, the importance of actinic Metrology and Inspection systems is increasing, and EUV light sources with high brightness and high availability are required. Gigaphoton Inc. has been developing laser-produced plasma (LPP) EUV light sources using Sn droplet technology for exposure tool since 2000. Based on this accumulated LPP EUV source technology, we have developed a High-brightness and compact LPP EUV source for Metrology and Inspection systems. This newly developed light source is a SoCoMo (Source Collector Module) EUV light source with a built-in reflective mirror based on customer specifications. In addition, it features stable operation and a one-year maintenance-free structure, contributing to longterm stable operation of the inspection equipment. Currently this EUV light source has demonstrated a brightness of 120W/mm2sr at the plasma point at a repetition frequency of 20kHz without any decrease in reflectivity of the EUV collector mirror after 500 hours of operation.

As chip feature sizes have continued to shrink, resolution enhancement techniques such as Optical Proximity Correction (OPC) have been utilized in advanced technology nodes. In recent years, Inverse Lithography Technology (ILT), a new OPC technique, has been widely applied in advanced Logic and Memory applications to improve imaging performance. Compared to the conventional OPC, ILT enables better process windows (PW) with low edge placement error (EPE) and high wafer critical dimension uniformity (CDU), etc. However, the nonrectilinear mask shapes in ILT make mask writing extremely complex and slow, which can potentially cause more mask manufacturing errors. Therefore, it’s important to quantitatively study the MEEF in ILT masks. In this work, we studied the MEEFs of 2D patterns corrected by ILT and conventional OPC and the differences between these two techniques. The results show that the MEEF at different positions (local MEEF) on an ILT mask has a bigger mean of ~3.14 and a smaller σ of ~0.09 relative to the mean of ~2.14 and σ of ~0.67 from a conventional OPC mask. The MEEF budget is analyzed based on the separated main features (MF) and subresolution assist features (SRAF). With SRAFs being inserted into the entire layout of the ILT mask, it contributes to all individual patterns with ~ 45% (1.49) of the total MEEF. Meanwhile, a conventional OPC mask only has SRAFs on the edges. Thus, SRAFs only contribute MEEF to the patterns located in the edge region (within the proximity effect range). Thus, the main center region of the OPC Mask has a lower MEEF contribution (~1.7). These results suggest that in the ILT recipe tuning process, MEEF should also be included in the cost function as a nonlinear factor so that the inversion can minimize MEEF while optimizing PW and EPE. Furthermore, the manhattanization of the ILT Mask can effectively reduce MEEF.

As semiconductor device fabrication moves towards 2 nm technology nodes with EUV lithography, new EUV absorber materials will be needed to replace the current Ta-based EUV photomasks. The industry is looking for new absorber materials with a low refractive index (n) and a high extinction coefficient (k), to produce an attenuated phase-shift EUV photomask capable of minimizing 3D effects. The challenge is that these new materials are often difficult to etch. To identify the etching pathway for new EUV material candidates, this paper proposes the approach of thermodynamic characterization for various chemistries as etching byproducts. The Gibbs free energy of formation for these compounds can be collected at standard state conditions, so the potential for such chemical reactions can be evaluated. Meanwhile, the volatility of these reaction products can be estimated by the respective boiling points, which can be calculated from respective heats of vaporization at reduced pressures typically found in a plasma etch chamber. Collectively, this information can help to screen for new low-n / high-k absorber materials, to focus the selection only to candidates with potential etching feasibilities.

With the continuous development of advanced semiconductor technology, the critical pattern shrinkage stably in integrated circuits has become a crucial step for product performance improvement and power consumption reduction. Compared with EUV technology, ArF immersion lithography of DUV is still the most popular research for advanced wafer fabrication, which makes the local critical dimension uniformity (LCDU) improvement become challenging for continuous pattern shrinkag. In the known research, LCDU for small hole pattern is affected by various factors, such as MEEF/OPC model/pattern density on mask and litho/Etch/Metrology process and so on. In the previous study, the improvement of wafer LCDU could be achieved by reducing MEEF of using HT PSM mask. On this basis, we also studied a new type of low sensitivity photoresist for HT PSM mask, which has better performance in controlling LER and LWR. In the meantime, compared with the actual performance of mask LCDU, it is verified that this new photoresist has obvious improvement. This paper mainly studies and compares the differences between the new low sensitivity photoresist and traditional photoresist, and conducts experiments to verify its performance on mask LCDU with extreme small hole patterns. It was found that the LCDU of the mask using new photoresist is improved by ~12%. Furthermore, in the actual application of fab production, the wafer LCDU is improved about 6~10%, and the pattern resolution and profile have also been improved to some extent, this research has played an important role in the development of advanced semiconductor processes.

Over the past years, we have demonstrated that off-line mask registration measurements as measured by the Zeiss PROVE tool correlate very well (R2 > 0.96) with the on-wafer measurements. The first correlation study was based on scanner wafer alignment marks. Wafer alignment marks are metrology structures that can be readout by the alignment sensor inside the scanner. After we established the correlation, we continued the investigation by exploring overlay metrology targets. Also in this case, a very good correlation (R2 > 0.92) was found in the sub-nanometer regime. This could be achieved due the fact that overlay metrology targets are much smaller in size compared to the scanner wafer alignment marks. This enables the possibility to measure basically the same target areas by the PROVE and the ASML Yieldstar (YS:375) overlay metrology tool. The resulting residual level between mask and on-wafer measurements was less than 0.14-nm (99.7%) at wafer level (1×). The small mismatch that was remaining could be attributed to local mask writing variations inside the overlay metrology targets. The local variations triggered us to consider the mask writing impact on the placement errors for individual device features. Even for this case at device level, a very good correlation was observed between the mask registration measurements and the on-wafer results. This time, the on-wafer results were obtained by using a large field-of-view SEM. From all the findings above, we can basically conclude that off-line mask registration measurements can be used as overlay predictors in a production environment. This enables computational overlay metrology from scanner alignment marks, to overlay metrology targets, down to single device features. It might be obvious that these findings could be very helpful in predicting the mask overlay contribution as part of the intra-field overlay contribution without actually performing the onwafer measurements and consequently reducing the fab cycle time. At this point, we would like to zoom out and consider how all the acquired knowledge can be utilized in a production environment. Basically, the mask-related local placement errors of all features within the exposure field on a wafer can be predicted accurately based on off-line mask measurements. However, before improving the on-product overlay and hence the yield, more insight is required on how the mask writing fingerprint looks like. Do we see a global fingerprint or do local effects dominate the fingerprint? Is the fingerprint the same for the overlay metrology targets and device? Or do we observe a metrology to device (MTD) offset? In this paper, we will show a dense characterization of the mask registration fingerprint. Off-line measurements were done on overlay metrology targets as well as on a structure representing the device pattern. We will show how the overlay metrology sampling layout selection will impact the device overlay performance. Based on this understanding, we aim at providing a strategy and a path forward on how to mitigate the mask related MTD offsets.

In EUV lithography, resolution enhancement techniques are applied for manufacturing and also studied actively to improve resolution. Among them, PSM is one of the key technique to improve the resolution limit in the conventional lithography. In this study, we investigated the novel EUV absorber material regarding to imaging properties and patterning process. In simulation tool PROLITH, the reflectivity of novel absorber material PSM was about 9%. As a result, this PSM structure shows better normalized image log slope(NILS) and image contrast. In addition, new PSM structure shows better process friendly properties such as etch rate and PSM profile compared to the conventional Rubased PSM that is currently being actively studied.

In this paper, we present the development of a new Multi-PNG (mPNG) format for efficient representation of full mask spatial maps (density map, dose map and/or geometric property map). The mPNG consists of multiple independent, interconnected and spatially non-overlapping PNG files, where each PNG file contains the density map for a unique section of the mask area (such that the full mask area is covered through the assembly of all files). Further, the paper will present mPNG file sizes and generation runtimes on full mask data for varying density map grid sizes that are relevant for correcting long range mask process effects in the sub-micron to millimeter range.

Recently, Ising machines, which solve Quadratic Unconstrained Binary Optimization (QUBO) problems in a short computation time, have attracted attention. In this paper, we propose a mask optimization method using an Ising machine to obtain a mask with high fidelity to target patterns and high tolerance to process variation. In the proposed method, a mask pattern is improved by repeatedly solving QUBO problems by the Ising machine. In experiments, we applied the proposed method using the Ising machine to various patterns and evaluated it in comparison with existing methods in fidelity to target patterns, tolerance to process variation, and execution time.

While the curvilinear mask shapes generated by ILT improve the wafer lithography process window, the efficiency of mask data preparation steps and the MBMW data-path depends on the number of edges used to represent complex curvilinear shapes. Shape simplification methods have been shown to be effective in reducing the number of edges used to represent curvilinear mask data. In this paper, we present the development of an approach to analyze the impact of edge-length variation on curvilinear mask accuracy, which can be used as a practical guidance for edge-based representation of curvilinear shapes for a given mask process.

Instead of using the inverse lithography technology (ILT) flow that allows for unrestricted shapes and widths of sub-resolution assist features (SRAFs), Y. Xu et al. propose an alternative approach. This method involves the direct specification of width, curvature, and minimal area to generate constant width curvilinear SRAFs. The study described in Ref. 1 demonstrates several advantages associated with constant width curvilinear SRAFs compared to their freeform counterparts. The advantages include improved compliance with manufacturing rule check (MRC) requirements, mitigation of SRAF printing issues, compatibility with the tile boundary stitching, enhanced runtime robustness, and better control over data volume. In the field of mask process correction (MPC), it is worth examining the potential advantages offered by constant width curvilinear SRAFs. Since all SRAFs must be printed on the mask but not on the wafer during the manufacturing process, the goal of MPC is the same for main features and SRAFs, aiming to ensure that patterns on the fabricated masks align precisely with target shapes and minimize edge placement errors (EPEs). This paper presents a comprehensive study of MPC accuracy and runtime performance when employing constant width SRAFs as input. A comparative analysis is conducted against the use of freeform SRAFs. Various MPC approaches, such as shape-based and dose-based corrections, treating SRAFs as a visible layer without edge bias, curvature-based prebias (CBB), and curvature-based fragmentation (CBF) are explored. The findings of this study provide valuable guidance for the generation of masks with constant width curvilinear SRAFs.

Stage positioning accuracy in mask writers and metrology equipment is typically stated as a single number by equipment manufacturers (average plus 3-sigma value). The error budget that constitutes this specification is seldom discussed with equipment purchasers and is usually confined to the equipment manufacturer and their suppliers. Interferometer subsystems consist of multiple technical disciplines including stable wavelength laser technology, optomechanics (interferometers), detectors, electronics, and algorithms (phase measurement and interface electronics). Each technology has significantly advanced since the introduction of laser interferometry on mask and wafer lithography and metrology equipment. This paper discusses the error budget related to the interferometry subsystem and possible improvements to this subsystem going forward.

Extreme ultra violet lithography is one of the most promising technologies for next-generation and already applied to critical layers for imaging 7-nm node and beyond. On the other hand, immersion ArF (iArF) lithography also continues to be applied to some critical layers by utilizing Multiple Patterning (MP). High accurate overlay control is required to reduce Edge Placement Error (EPE). In general, global errors on mask such as Critical Dimension Uniformity (CDU) and Image Placement (IP) are known as critical factors affecting EPE. Recently, the local variations on wafer are also discussed as non-negligible factors, especially for advanced technology node. Local CDU (LCDU) is one of the most typical local variations, therefore its requirements are getting more severe. In this paper, the mask impact on wafer LCDU in ArF lithography was investigated. In order to characterize the mask contribution, we designed the mask which has the patterns with various mask LCDU and lithographic performances. According to these evaluations, it was confirmed that mask LCDU, Normalized Image Log Slope (NILS) and Mask Error Enhancement Factor (MEEF) are major contributors to wafer LCDU. Based on the results, we explored wafer LCDU improvement by mask optimization and demonstrated its benefit on wafer.

A significant proportion of the world’s photomasks are written by the ALTATM i-line laser mask writers that started shipping in 1994. Many of these masks are used for manufacturing devices in the growing “ICAPS” markets: the Internet of Things, Communications, Automotive, Power and Sensors. Every ALTA i-line writer shipped is still in production due to sustained investments, driven by the motivation to keep fully depreciated equipment running as long as possible. Technology developments recently created the opportunity for a comprehensive renewal of this installed base. A field upgrade package has been developed that replaces the legacy computing systems and electronics with modern equivalents, while substantially reducing the power consumption and significantly increasing productivity. The software-based data path developed for ALTA DUV laser mask writers has been ported to iline, bringing an order of magnitude increase in processing speed for data prep and rasterization compared to the original hardware-based method. The data path accepts MEBES, OASIS and GDSII data formats, and the 33x (0.8 NA) system outputs data on a grid reduced to 0.625 nm. The new data path also provides optionally-enabled compensation for process footprint and pattern-density related CD errors, and the multicore server accounts for a large share of the system speedup. Another improvement adopted from the DUV writer is an axis-parallel, 32-beam brush with a new scan lens, enabling a novel bidirectional writing scheme that minimizes overhead time and contributes to the increased writing speed. The legacy gas laser has been replaced with a solid state, optically pumped semiconductor laser (OPSL) designed to match the original wavelength, reducing system power consumption by about 75%.