Extremely low-noise 0.15 m gate-length V- and W-band InGaAs / InAlAs / InP lattice-matched and pseudomorphic HEMTs have been successfully fabricated. A maximum extrinsic transconductance of 1,500 mS/mm and a gate breakdown voltage of more than 10V have been obtained for the devices. Minimum noise figures of 0.3,0.9 and and 1.4dB have been measured for the devices at 18,60 and 94GHz, respectively. We have also measured a maximum available gain of 13.6dB at 95GHz, corresponding to a maximum frequency of oscillation, fmax, of 455GHz (-6dB/octave extrapolation) with the device. Based on these high performance 0.15?m devices, a 3-stage hybrid amplifier with a minimum noise figure of 3.3dB and gain of 17.3±0.5dB from 88 to 96GHz has been built. We have also successfully demonstrated for the first time a two-stage InP-based HEMT monolithic microwave integrated circuit (MMIC) with 3.0dB noise figure and 21.0dB gain at 58GHz. These are the best device and amplifier results ever reported. The results are far superior to those obtained from the GaAs-based MESFET and HEMT technology, and clearly demonstrate the potential of the InP-based HEMT technology for very low-noise applications well into the millimeter-wave regime.

This paper discusses the non-saturating GaAs/AlGaAs N-p-n heterojunction bipolar transistor (GaAs HBT) technology and circuit applications where the GaAs HBT offers unique advantages. A relaxed 2-3 ?m emitter self-aligned HBT IC process and molecular beam epitaxial structure developed at TRW for producibility, permit simultaneous fp, fmax ? 30-60 GHz, dc current gain ??50-100, and MSI-LSI integration levels. It is used as a vehicle for demonstrating initial technology capabilities including dc to 20 GHz analog/microwave, 3-6 GHz digital, and 1-3 GHz analog/digital conversion, as well as monolithically- combined functions. Significant improvements are realized over advanced Si bipolar and GaAs field-effect transistor approaches in combinations of operational frequency, power consumption, gain-bandwidth product, harmonic distortion, phase (1/f) noise, and radiation hardness. These capabilities along with the GaAs HBT technology’s extensive growth potential should assure its future competitiveness as well as its expanding role in achieving more efficient system functions.

A novel self-aligned technique for 0.15 ?m gate length AlInAs-GalnAs HEMTs has been demonstrated. Devices with an oxide sidewall yielded an fT of 177 GHz whereas devices with no sidewall exhibited an fT greater than 250 GHz. The difference has been related to process damage during plasma deposition of SiO2. An extrinsic fT of 292 GHz was measured at 77K.

Extracted delay times provide information useful for device scaling. In this work a novel parameter extraction technique that permits delay times associated with the physical operation of the transistor, along with element values for an equivalent circuit, to be determined from terminal S-parameter measurements. The technique is employed to investigate the operation of mm-wave AlInAs/GalnAs/InP heterojunction bipolar transistors. High current phenomena, such as the onset of the Kirk Effect, are clearly evident. The results indicate that the base region delay is dominant in determining the high frequency operation of these devices.

Ultra thin (100-200 Å) AlGaAs emitter layers have been incorporated in AlGaAs/GaAs Heterojunction Bipolar Transistors (HBTs). Fabricated using a self-aligned process technology, this novel structure has yielded transistors with submicron emitter widths. The AlGaAs emitter layer serves to passivate the base surface resulting in constant current gain values of 25 for all geometries independent of emitter area. The maximum cutoff frequency obtained was 35 GHz with a corresponding 38 GHz for the maximum frequency of oscillation for a 1.3?m x 9 ?m emitter area device.

This paper describes the demonstration of CML ring-oscillators and static frequency divider circuits implemented with AlInAs/GalnAs heterojunction bipolar transistors (HBTs) lattice matched to InP substrates. A cutoff frequency (fT) and a maximum frequency of oscillation of 90 GHz and 70 GHz, respectively, have been achieved with a 2x5-?m2 emitter. The ring oscillators demonstrated a 15.8 ps gate delay. The divider circuits were clocked at 24.8 GHz.

As III-V device fabrication technology continues to improve and performance limiting parasitics are eliminated, the intrinsic speed of any given device structure and options for increasing that speed are of greater interest to device researchers and technologists. One approach to improving heterojunction bipolar transistor (HBT) high-frequency performance is to reduce the transit time across the collector space charge region by carefully tailoring the electric field in the collector in such a fashion as to extend or enhance velocity overshoot in the space charge region. This technique was first described1 and demonstrated2-3 for AlxGa1-x As/GaAs HBTs. Recently, structures composed of materials lattice matched to InP substrates4-5 have emerged as champions in the race for high-speed and optical applications honors. Because these devices have utilized conventional collector structures, further gains can be achieved by application of collectors designed for enhanced or extended velocity overshoot. This is easily seen by noting that the extended velocity overshoot condition is more easily achieved in In0.53Ga0.47 As than in GaAs, in large part due to the larger ? — L conduction band separation (?E?L — 0.55 eV for In0.53Ga0.47AS; ?E?L = 0.33 eV for GaAs). In this paper, we present Monte Carlo simulation results demonstrating the efficacy of the extended velocity overshoot approach for reducing transit times across the collector for a number of ln0.53Ga0.47As collector structures.

Npn InAIAs/InGaAs abrupt heterojunction bipolar transistor (HBT) structures were grown on InP substrates, by the molecular beam epitaxy (MBE). Transistors were fabricated by using a non-self-aligned technology which uses a selective wet etching to reach the base layer. DC measurement showed that the base current was dominated by the depletion region recombination in the base-emitter junction. CV measurement showed a lot of defects in the heavily compensated InAIAs emitter. The collector current densities for the different layers correlated with the CV measurement results. The microwave measurements on the 4 ?m x 5 ?m emitter InAIAs /InGaAs HBT resulted in ft and fmax of 47 GHz and 27 GHz, respectively. The bias scan and the S-parameter measurement showed that the microwave performance of the device was limited by the parasitic resistance in the emitter, which was much bigger than the emitter contact resistance. This extra emitter resistance was due to the undepleted and heavily compensated InAIAs emitter. A physical small signal circuit model showed that in the absence of this extra emitter resistance, f{ would become more than 70 GHz. A much better performance is expected with a higher InAIAs emitter dopings, such as 1x1018 cm-3, which reduces the extra parasitic resistance in the InAIAs emitter significantly.

The monolithic integration of complementary AlGaAs/GaAs heterojunction bipolar transistors (HBTs) has been accomplished using selective MOVPE to regrow an Npn HBT on a Pnp HBT waler. A non-self- aligned mesa process was used in fabricating the transistors. Pnps (Npns) with a. minimum geometry emitter of 6?m by 12?m yielded a current gain of 300 (75) which was not degraded by the regrowth process and an ft of 2.5 (22) GHz. An inverting amplifier with feedback for unity gain, a push-pull emitter follower and a complementary Gilbert Gain Cell amplifier were fabricated and tested indicating the feasibility for high speed (Al)GaAs HBT operational amplifiers (op-amps).

AlGaAs/GaAs Pnp HBTs have the potential for high frequency performance approaching that of Npn HBTs. To achieve this performance, it is necessary to dope the base as heavily n-type as possible. This heavy base doping results in large degeneracy in the base, which reduces the heterobarrier to reverse injection of electrons from the base into the emitter. High A1 content in the emitter is desirable to maintain good injection efficiency. Incorporating a gradient in the base doping can introduce fields to sweep injected holes across the neutral base region, which reduces base transport time. DC and RF characteristics of Pnp HBTs with 40% and 75% Al in the emitter will be presented. ft of 17 GHz and fmax of 39 GHz has been achieved in 2 ?m x 11 ?m HBTs fabricated using a self-aligned ohmic contact process. Further improvement in performance should be possible.

The microwave power performance of AlGaAs/GaAs self-aligned HBTs from 10 to 35 GHz is described. A record value of 68% power added efficiency was obtained at 10 GHz. At 18 GHz, 16.3 dB associated gain was achieved with 1.83 W/mm power density and 40% efficiency. At 35 GHz, a 15 dB small signal gain was observed. The tested HBTs have 2 micron feature size. Further improvement is expected with optimization of the HBT structure.

New double-barrier resonant-tunneling diodes have been fabricated in the pseudomorphic In0.53Ga0.47As/AlAs material system that have peak current densities exceeding 1x105 A cm-2 and peak-to-valley current ratios of approximately 10 at room temperature. One of these diodes yielded oscillations up to 125 GHz, but did not oscillate at higher frequencies because of a large device capacitance. A device with a much lower capacitance is estimated to have a maximum oscillation frequency of 932 GHz and a voltage rise time of 1.5 ps in switching from the peak bias point to the valley bias point. Other reported In0.53Ga0.47As/AlAs diodes are analyzed and yield theoretical maximum oscillation frequencies over 1 THz and rise times as low as 0.3 ps.

Planar, interdigitated In0.53Ga0.47As/GaAs finger structure resonant tunneling diodes (RTDs) have been successfully fabricated on the semi-insulating InP substrate by using a novel self-alignment and air-bridge technique. This design significantly reduces the parasitic series resistance, increases the oscillation frequency, and reduces the power loss. The front-side contact scheme also enables the monolithic integration of the RTDs in series to achieve multiple negative differential resistances.

The existence of negative resistance in double barrier resonant tunneling structures has led to the proposal of various applications for these devices. For many of these applications, stability is an important consideration. This paper will discuss the effect that various device parameters have on stability and on the capability of high frequency device operation. It is concluded that the circuit and device conditions required for stable operation greatly reduce the amount of power that can be produced by these devices at microwave and millimeter-wave frequencies.

For Si1-xGex/Si hole and Ga1-xAlxAs/GaAs electron double barrier resonant tunneling devices (RTDs), we have studied the negative differential resistance (NDR). The current peak-to-valley ratio (PVR) was investigated as function of the temperature T for different device parameters and the dependence of the maximum working temperature Tm on material parameters and device parameters was determined. The results show that by narrowing well and barrier width, decreasing barrier height, and decreasing the doping concentration in the spacer layer, the RTDs have improved temperature characteristics, and have higher peak current Jp and larger PVR at high temperature. The RTDs with larger well width, and wide and high barriers nave quite large PVR, and are favorable to use at low temperature. Ga1-xAlxAs/GaAs electron RTDs are estimated to work at room temperature for a wide range of device parameters, while the device parameter design of Si1-xGex/Si hole RTDs is much more critical to work at same temperature. These results are consistent with the tendency of recently published experiments. On the basis of calculated PVR curves we can optimize RTD parameters to increase the working temperature and current peak-to-valley ratio.

Three models are presented for resonant tunneling diodes (RTD). These models range in complexity from a full quantum kinetic equation based on the Crystal Wigner function approach to a simple phenomenological model based on the drift-diffusion equation. Of these three, the Crystal Wigner function has the capability of properly accounting for complex band structure transport issues within the quantum well region.

Atomic layer epitaxy (ALE) has been used for the low temperature deposition of planar-doped structures using organometallic sources, AsH3 and H2Se. Carrier concentrations in the 1019/cm3 range have been achieved, with a sharp concentration profile comparable to that reported for equivalent structures by molecular beam epitaxy (MBE). A set of planar-doped Se sheets, separated by 50 A of undoped GaAs, was used for nonalloyed contacting layers to n-GaAs films with contact resistivity in the low 10-6?cm2 range. The sidewall regrowth capability of ALE was also used in reducing the parasitic source and drain resistances by about 30%. Finally, a planar doped field effect transistor (FET) were fabricated. The performance of these ALE devices were comparable to FET devices fabricated by other growth techniques.

Ultra-submicron gate GaAs MESFETs and AlGaAs/GaAs HEMTs have been fabricated in an electron- beam lithographic process with gate lengths varying from 25 to 80 nm. For gate length less than 100 nm, electrical characteristics deteriorate due to fringing capacitance at a low aspect ratio. Velocity overshoot is observed for gate length shorter than about 55 nm. The maximum effective electron saturation velocity obtained is 3x107 cm/sec for a 30 nm HEMT. A maximum fT value of 167 GHz was obtained for a 37.5 nm MESFET.

Studies of current-voltage (I-V) characteristics and their temperature dependence show that the current transport in MBE-grown Si1-xGex/Si diodes is closely related to the epitaxial film quality. It is mainly controlled by two different mechanisms at low and high temperature. The ideality factor n of the diodes increases as the temperature is reduced, and n increases faster for the diodes which have larger n at room temperature. From comparisons with calculated results, it is proposed that the transport mechanism is diffusion controlled at high temperature and defect-assisted tunneling controlled at low temperature. The results from ? irradiation studies also support this suggestion. Due to the existence of band-offsets, the shift of the I-V curve with temperature of p+-Si1-xGex/n-Si diodes is much smaller than that in n+-Si1-xGex/p-Si diodes, when the current is diffusion controlled. The band-offsets are estimated from these shifts, and the results are in agreement with values measured by another method.

The Modulation Doped Transistor (MODFET) has recently achieved its predicted performance goals, thus demonstrating its potential for providing the semiconductor transistor component necessary for future high speed and millimeter wave integrated systems. This high performance has been achieved through i) the optimization of MBE growth of pseudomorphic heterojunctions, ii) modifications to the epitaxial layer design based on new physical insight into the operation of MODFET structures at high frequency and iii) improvements in the FET fabrication and “layout” structure (geometry) to minimize resistive and reactive parasitic impedances.

Parasitics must be reduced for mm-wave MODFETs to realize their high potential. The parasitic resistances must be reduced so that (1) parasitic charging time is negligible, (2) to maintain the fj/fmax ratio, and (3) noise figure and power performance are not degraded significantly. The parasitic resistance must be scaled as l/fj. The problem of backside via inductance dominating the effective input resistance of wide MODFETs is shown. The design compromises are discussed, and rules-of-thumb are presented for scaling parasitics, (e.g., T-gate size).

AlGaAs/InGaAs/GaAs pseudomorphic HEMTs with an InAs mole fraction as high as 35% in the channel has been successfully fabricated. The device exhibits a maximum extrinsic transconductance of 700mS/mm. At 18GHz, a minimum noise figure of 0.55dB with 15.0dB associated gain was measured. At 94GHz, a minimum noise figure as low as 2.4dB with 5.4dB associated gain was also obtained. This is the best noise performance ever reported for GaAs-based HEMTs.

A novel adaption of the mushroom gate structure has been realized and exhibited in MESFET as well as HEMT devices. The gate structure has a serrated appearance, and it realizes low input capacitance, in addition to the low resistance achievable using a conventional approach. At gate lengths below 0.15 micron, the device structure assumes a qualitatively different form, requiring a reassessment of the scaling rules. Initial results on working devices are presented.

This paper describes the scaling of High-Electron Mobility Transistors (HEMTs) for ultra-high-speed operations. We predict that, with proper device scaling, an extrinsic switching speed in excess of 300 GHz will be achieved in the near future for state-of-the-art HEMTs.

The 80 K noise performance of the In0.53Ga0.47As/InP modulation-doped field- effect transistor (MODFET) grown by organometallic vapor phase epitaxy (OMVPE) is investigated. MODFETs are fabricated by incorporating the gate-insulating InP layer, double modulation doping scheme, and a burned p-buffer layer into the structure design. Improvements in both the drain and gate breakdown voltages are achieved in the present MODFET design. We demonstrate for the first time the low noise performance in the InGaAs/InP MODFET system with high breakdown voltages. Measuring the 0.3?m-gate devices at 10 GHz and 80 K, a minimum noise figure of 0.26 dB with an associated gain of 10.23 dB was observed. The low cryogenic noise figure is attributed to the reduced parasitics, good carrier confinement, reduced scattering, high electron mobilities and velocities. The microwave and noise performance clearly indicate the advantage of InGaAs channel for carrier transport. The noise measurement serves as a useful technique to detect the onset of ionization processes at high drain potentials.

We propose a new Heterostructure Field Effect Transistor (HFET) structure. The proposed device is a quantum-well HFET with a p+ gate and fairly heavily doped p-type buffer. We call this device a TC-HFET meaning p-type Insulated gate HFET. The effective barrier height in a TC-HFET is considerably larger than in other compound semiconductor FETs and the gate current and real space transfer problem at maximum gate voltage swing can be made negligible even at room temperature. Based on the trade-off between the noise margin and speed, we propose 0.7 V and 1.5 V as the minimum power supply voltages for the direct coupled FET logic at 77 and 300 K, respectively. Our calculations demonstrate that this TC- HFET technology can meet all requirements for VLSI applications and that high electron velocity and mobility in TC-HFETS lead to an increase in speed of output drivers by a factor of four at 77 K and a factor of 10 at 300 K (compared to Si NMOS which is faster than CMOS). The full advantages of TC-HFET technology can be only realized on a submicron scale where source and drain series resistances play a dominant role in determining the noise margin. This leads to the necessity to modify both the device design and fabrication process for better control of series resistance uniformity. In order to reduce the series resistances, we propose new self-aligned fabrication processes for TC-HFETS such as a modified SAINT process and a modified T-gate process.