CONFERENCE PROCEEDINGS
Advanced Search
Home > Proceedings > Volume 12954 > Article
Presentation + Paper
10 April 2024 Investigation of die-cost scaling scenarios in future technologies
G. Mirabelli, Y.-P. Tsai, Y.-H. Chang, D. Velenis, R.-H. Kim, J. Myers, L.-Å. Ragnarsson, O. Zografos, G. Hellings
Author Affiliations +
Proceedings Volume 12954, DTCO and Computational Patterning III; 129540E (2024) https://doi.org/10.1117/12.3010149
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States
Abstract
The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.
Conference Presentation
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Citation Download Citation
G. Mirabelli, Y.-P. Tsai, Y.-H. Chang, D. Velenis, R.-H. Kim, J. Myers, L.-Å. Ragnarsson, O. Zografos, and G. Hellings "Investigation of die-cost scaling scenarios in future technologies", Proc. SPIE 12954, DTCO and Computational Patterning III, 129540E (10 April 2024); https://doi.org/10.1117/12.3010149
ACCESS THE FULL ARTICLE
ORGANIZATIONAL
Sign in with credentials provided by your organization.
INSTITUTIONAL
Select your institution to access the SPIE Digital Library.
SELECT YOUR INSTITUTION
PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.
PERSONAL SIGN IN
No SPIE Account? Create one
PURCHASE THIS CONTENT
SUBSCRIBE TO DIGITAL LIBRARY
50 downloads per 1-year subscription
Members: $195
Non-members: $335 ADD TO CART
25 downloads per 1 - year subscription
Members: $145
Non-members: $250 ADD TO CART
PURCHASE SINGLE ARTICLE
Includes PDF, HTML & Video, when available
Members: $17.00
Non-members: $21.00 ADD TO CART
PROCEEDINGS
 7 PAGES + PRESENTATION
DOWNLOAD PAPER SAVE TO MY LIBRARY
WATCH
PRESENTATION
GET CITATION
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Back end of line
Front end of line
Logic
Semiconductor manufacturing
RELATED CONTENT
Subscribe to Digital Library
Receive Erratum Email Alert
Back to Top