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9 April 2024 Machine learning methods for voltage contrast yield analysis
D. Cerbu, V. M. Blanco Carballo, F. Schleicher, J. van de Kerkhove, P. Leray, N. N. Kissoon, E. P. De Poortere
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Proceedings Volume 12955, Metrology, Inspection, and Process Control XXXVIII; 129551C (2024) https://doi.org/10.1117/12.3011142
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States
Abstract
In the manufacturing of CMOS devices, the golden standard for determining yield at various stages of production is electrical testing. This allows for the identification of failing devices or early yield failures before proceeding to subsequent steps. However, the failure of electrical tests can occur due to various reasons inherent to the structures of the devices. Additionally, a comprehensive analysis is necessary to ascertain the root cause of the failure mechanism once a device does not pass the electrical tests.
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D. Cerbu, V. M. Blanco Carballo, F. Schleicher, J. van de Kerkhove, P. Leray, N. N. Kissoon, and E. P. De Poortere "Machine learning methods for voltage contrast yield analysis", Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 129551C (9 April 2024); https://doi.org/10.1117/12.3011142
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KEYWORDS
Machine learning
Semiconducting wafers
Design
Image processing
Scanning electron microscopy
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