1 September 1990 Design and implementation of moment invariants for pattern recognition in VLSI
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Abstract
This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in pattern recognition. The pattern recognition scheme uses Hu1 and Mailra''s2 algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. Use of the Manchester carry chain effectively incorporated the lookahead carry function into the adder cells. The prototype ASIC is currently being fabricated in 2. 0-mm compiled simulator for metal oxide semiconductor (CMOS) technology (simulated at 20 MHz). The prototype consisted of a 4x8 multiplier and a 12-bit accumulator stage. The present ASIC design consists of a 9x26 multiplier (maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 56 MegaPixels/s [230 million operations per second (MOPs)] necessary to perform the moment invariant algorithms in real time on 512x512 pixel images with 256 grey scales. 2.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gary A. Armstrong, Marc L. Simpson, Donald W. Bouldin, "Design and implementation of moment invariants for pattern recognition in VLSI", Proc. SPIE 1297, Hybrid Image and Signal Processing II, (1 September 1990); doi: 10.1117/12.21319; https://doi.org/10.1117/12.21319
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KEYWORDS
Clocks

Image processing

Prototyping

Pattern recognition

Signal processing

Very large scale integration

Algorithm development

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