1 September 1990 640 x 480 element PtSi IR sensor with low-noise MOS X-Y addressable multiplexer
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The design of a 640 by 480 element PtSi IR sensor is presented which includes a low-noise MOS X-Y addressable readout multiplexer and an on-chip correlated double-sampling amplifier. The sensor is designed to load scan data into CMOS horizontal and vertical scanning registers by means of a multiplexed horizontal/vertical input address port and onchip decoding, allowing any element in the focal plane array to be randomly accessed. The FPA is shown to be operable in both the interlaced and noninterlaced formats, with variable exposure control. Enhanced noise performance is shown due to the use of buried channel source follower buffers in the horizontal signal lines. It was shown that 24 micron square pixels with a 1.5 micron double level metal CMOS process provide a fill factor of 38 percent. TTL compatibility and ESD protection diodes are key features of the digital inputs to the sensor's chip.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Donald J. Sauer, Donald J. Sauer, Fu-Lung Hseuh, Fu-Lung Hseuh, Frank V. Shallcross, Frank V. Shallcross, Grazyna M. Meray, Grazyna M. Meray, Thomas S. Villani, Thomas S. Villani, } "640 x 480 element PtSi IR sensor with low-noise MOS X-Y addressable multiplexer", Proc. SPIE 1308, Infrared Detectors and Focal Plane Arrays, (1 September 1990); doi: 10.1117/12.21719; https://doi.org/10.1117/12.21719


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