Design of a high-speed optical arithmetic unit

Susamma Barua

doi:10.1117/12.23440

27 December 1990 Design of a high-speed optical arithmetic unit

Susamma Barua

Proceedings Volume 1347, Optical Information Processing Systems and Architectures II; (1990) https://doi.org/10.1117/12.23440
Event: 34th Annual International Technical Symposium on Optical and Optoelectronic Applied Science and Engineering, 1990, San Diego, CA, United States

Abstract

The design of a high-speed, parallel arithmetic unit using the redundant binary representation is presented. The arithmetic unit consists of an adder and multiplier. The adder performs the addition/subtraction of two numbers in a single stage independent of the length of the numbers and the multiplier performs the multiplication in a computation time of O(log n) with O(n squared) computational elements.

Citation Download Citation

Susamma Barua "Design of a high-speed optical arithmetic unit", Proc. SPIE 1347, Optical Information Processing Systems and Architectures II, (27 December 1990); https://doi.org/10.1117/12.23440

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