The design of a high-speed, parallel arithmetic unit using the redundant binary representation is presented. The arithmetic unit consists of an adder and multiplier. The adder performs the addition/subtraction of two numbers in a single stage independent of the length of the numbers and the multiplier performs the multiplication in a computation time of O(log n) with O(n squared) computational elements.
"Design of a high-speed optical arithmetic unit", Proc. SPIE 1347, Optical Information Processing Systems and Architectures II, (27 December 1990); doi: 10.1117/12.23440; https://doi.org/10.1117/12.23440