1 November 1990 Efficient VLSI algorithm and an implementation architecture for gray-scale morphology
Author Affiliations +
This paper presents an efficient VLSI architecture for the real-time implementation of grayscale morphological operations. The proposed architecture employs a bit-serial approach which allows grayscale morphological operations to be decomposed into bit-level binary operations by a bit-modification algorithm, and thus requires only p binary operation units for the p-bit grayscale signal. In this realization, grayscale opening and closing are accomplished by local rather than cascade operations, providing greatly increased data throughput. It is shown that this realization is simple and modular in structure and is suitable for VLSI implementation.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sung-Jea Ko, Sung-Jea Ko, Malayappan Shridhar, Malayappan Shridhar, "Efficient VLSI algorithm and an implementation architecture for gray-scale morphology", Proc. SPIE 1350, Image Algebra and Morphological Image Processing, (1 November 1990); doi: 10.1117/12.23604; https://doi.org/10.1117/12.23604


Back to Top