Limitations of standard three-phase frame transfer CCDs in high-speed operation are discussed with particular attention given to parallel and serial transfer, and the output amplifier. It is noted that in most CCD designs the greatest limitation on high-speed performance occurs in a serial register. At very high clock frequencies (greater than 30 MHz) actual generation and transmission of the necessary pulses can become the dominant restriction. Multiple output registers make it possible to obtain much higher readout frequencies. Design of a high-speed device capable of being fully readout in less than 2 mS is presented.