1 September 1990 Parallel architecture for real-time video communications
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Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.35126
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland
Abstract
A video codec based on several parallel digital signal processors is described. The digital signal processors (DSPs) can be easily programmed to implement the H.261 algorithm and are organized as a single instruction multiple data (SIMD) computing architecture. Both the encoder and the decoder divide a picture in regions of horizontal strips and use one local processor per region. These local processors code (decode) one horizontal strip of data which, using the terminology of the H.261 standard, corresponds to two group of blocks (GOBs). They also communicate to a central processor which multiplexes (demultiplexes) the coded data from (for) the processors in the encoder (decoder). In the case of the encoder the central processor also controls a data buffer for bit-rate adaptation. Lateral communication between adjacent processors is implemented to allow comparisons between blocks situated in neighbouring regions, as required by most motion estimation algorithms.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Luis A. S. V. de Sa, Vitor Mendes Silva, Fernando Perdigao, Sergio Faria, Pedro Assuncao, "Parallel architecture for real-time video communications", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.35126; https://doi.org/10.1117/12.35126
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