1 September 1990 Principal devices and hardware volume estimation for moving picture decoder for digital storage media
Author Affiliations +
Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.24171
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland
Abstract
The ISO/MPEG has been discussing the establishment of a standard for moving- picture coding to ensure that digital storage media can store picture information efficiently. This paper introduces a trial design for the source decoder of simulation model 2 in the ISO/MPEG video subgroup. This paper describes MPEG simulation model decoding and the Fujitsu video signal processors, VSP-1 and DCT LSI chips. We designed a source decoder using these two LSI chips, memory, and standard logic ICs. The trial design showed that three VSP-ls and one DCT LSI chips are sufficient to make a source decoder.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Makiko Konoshima, Makiko Konoshima, Osamu Kawai, Osamu Kawai, Kiichi Matsuda, Kiichi Matsuda, "Principal devices and hardware volume estimation for moving picture decoder for digital storage media", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24171; https://doi.org/10.1117/12.24171
PROCEEDINGS
9 PAGES


SHARE
Back to Top