Continuing improvements in packaging and interconnect technology have made it increasingly difficult to adequately test printed wiring board (PWB) assemblies. Traditional PWB test methods depend on both the relatively small number of components on the board and easy access to the interconnection signal paths. This paper surveys options for verifying correct logical behavior (i. e. ''functional" or " digital'' testing) of state-of-the-art PWBs. Design for Testability (DFT) methods for enhancing circuit observability and controllability are described along with extensions of these methods for board-level testing (such as Built-In Self-Test and the IEEE/JTAG Boundary Scan standard). Testability problems are likely to increase as new packaging and interconnect technologies using ceramics and polyimides further increase circuit density and complexity. This paper considers the impact of these technology advances on current testing strategies and potential alternative methodologies.

This paper presents interconnection problems in VLSI Random Access Memory (RAM) chip. Interconnection effect on propagation delay speed power consumption and noise parameters are analyzed. Interconnect capacitance model is developed for VLSI RAM chip. A case study is presented for 1MB RAM chip interconnection problems. A multilevel interconnect approach is proposed to overcome onchip interconnect problems. The analysis results are found to be very useful for future mega bit RAMs. 98 / SPIE Vol. 1389 International Conference on Advances in Interconnection and Packaging (1990)

The performance of thin-film interconnections is influenced by the manner in which material selection and design rules interact with process capabilities. To understand this influence analysis of predicted and measured interconnection performance was correlated to design and process attributes. The models employed to predict propagation delay and noise are described and compared to experimental results. Attributes which contribute significantly to successful implementation of this technology are identified and accommodations in process controls and design rules are suggested.

High density interconnections are essential for high performance systems. For excellent signal fidelity it is essential to design interconnects as controlled impedance transmission lines in these systems. Results from design studies are summarized in this paper. Effects of substrate and conductor properties on the interconnect parameters are emphasized. Crosstalk noise is proportional to interconnection density. Crosstalk can be analyzed in SPICE using a set of isolated transmission line and congruence transformers synthesized with dependent sources A SPICE subcircuit for a pair of coupled interconnections is presented. Using this subcircuit crosstalk calculations are illustrated for systems based ECL and CMOS technologies. High density interconnects have considerable resistance. Results of a theoretical analysis of the time domain reflectometer (TDR) responses of a lossy interconnect are presented. These results can be used to determine the impedance and the effective resistance of the interconnections using a TDR. This technique is especially useful for digital systems using lossy transmission line approach.

A new transmission line configuration is presented for microwave and high-speed digital applications. The structure consists of a conducting strip over a triangular ground reference and offer superior electromagnetic performance at higher frequencies with lower radiation and lower coupling between neighboring interconnect lines. Parameters resulting from a static analysis are shown as a function of the geometrical characteristics and a full wave analysis is used to establish the frequency dependence of the propagation constant. Experimental results are compared with the theoretical data to validate the analysis and determine the advantages of the new structure.

Modern printed wiring board design depends on electronic prototyping using computer-based simulation and design tools. Existing electrical computer-aided design (ECAD) tools emphasize circuit connectivity with only rudimentary analysis capabilities. This paper describes a prototype integrated PWB design environment denoted Thermal Structural Electromagnetic Testability (TSET) being developed at Georgia Tech in collaboration with companies in the electronics industry. TSET provides design guidance based on enhanced electrical and mechanical CAD capabilities including electromagnetic modeling testability analysis thermal management and solid mechanics analysis. TSET development is based on a strong analytical and theoretical science base and incorporates an integrated information framework and a common database design based on a systematic structured methodology.

Theoretical time-domain results for sub-nano second pulse propagation along multiple coupled microstrip lines (MCMLS) are presented. Emphasis is placed on finding proper and realistic terminations for the MCMLS with minimal signal degradations in MMIC (millimeter-wave and microwave monolithic integrated circuits). An optimalload terminating condition considering electrical performance and cost effectiveness is tested and presented.

This paper discusses the maximum usable length (''max) for high-speed pulse propagation and its dependence on signal line resistance (R) for a range of wiring technologies. As an example we present results from measurements and analyses of experimental interconnection structures and their agreement is highlighted. The analysis is based on a transmission line model which includes frequency-dependent losses such as skin-effect and dielectric dispersion. The paper addresses the problems found on lossy lines such as reflections rise-time slow down increased delay attenuation and crosstalk. A wide bandwidth test system that relies on novel high frequency and high impedance coaxial probes which was developed to characterize our test structures is described. The limiting factors that affect circuitto- circuit path delays in high-performance computers are then discussed and guidelines are given for maintaining distortion-free propagation of high-speed signals. Simulations of resistive interconnections in a practical digital environment are presented.

This paper describes the analysis of switching noise in a 9-layer medium film copper/polyimide module. Equivalent circuit models which are used to understand and extend experimental results were constructed using a CAD tool which has been previously described. Results for this vehicle are used to study the dependence of noise magnitude on various module parameters including the number of switching gates the edge rate and the value and placement of bypass capacitance as well as assess the validity of various analytical switching noise models which have appeared in the literature.

Improved printed wiring board (PWB) manufacturing technology has resulted in more advanced methods for component mounting (such as surface mount technology). Evidence has shown that the new generation of PWBs cannot be built using surface mount technology (SMT) alone. Some passive components and connectors can only be mounted by using plated through holes (PTHs) and vias. Up to now PTHs and vias are still the most widely used inter-layer connections in a PWB. The advanced miniaturization technologies has dramatically reduced the size of a PTH to as small as 5mils and the use of multilayer composite construction further increases the level of design complexity. It has been determined that PTH failure results from thermo-mechanical deformation due to mismatch of coefficients of thermal expansion (CTE) in the out-of-plane (Z) direction between board substrate and the PTH copper plating at elevated temperatures. Although many studies have been conducted concerning the general PTH design what has not yet been evaluated in a systematic and comprehensive manner is the PWB failure resulting from copper barrel plating voids. A collaborative research effort between Georgia Tech and Motorola has recently been carried out to investigate the influence of voids on PTH failures. This study first identifies the basic key design parameters (such as void size void shape void location copper plating thickness etc. ) relevant to void characterization. These parameters with selected values were collectively formed a

The transmission of RF pulse through bend discontinuity in high speed integrated circuits is analyzed. The discontinuity bend is characterized by scattering parameters using the contour integral method. The modified planar model is applied as opposed to the conventional lumped element model. Transient response of the bend to RF pulse shows the quite different distortion of pulses propagating through the different kinds of bend and the optimum cut bend will provide the least distortion.

To shift the onset of skin resistance in off-chip interconnects novel microstructures are proposed as a method to maximize conductor surface area for a given pitch. We consider lines of Scm length operating at 1GHz with ~6dB attenuation. Assuming thin but wide lines (aspect ratio 10:1) for low distortion then conventional microstrip lines would require a 5Oim pitch theoretical study shows that a vertical coplanar line essentially a tall double-strip coplanar line could be packed twice as densely. Circuit theory and field theory which accounts for fringing are used to predict a reduction in high frequency resistance in laminated microstrip lines as well. Reduction in resistance was observed in a large-scale model of a transposed multiple-conductor microstrip line. Microfabrication of phase-velocity matched laminated lines demonstrated the difficulty of matching material constants emphasizing the relative strength of transposed laminated lines which do not require matching.

A novel developmental material for dielectric resonators has been characterized for use in microwave hybrid circuits. The material is in the form of a thin tape laminated on a conventional 96 alumina substrate. Significantly different experimental methods had to be employed for material characterization in the low frequency (10 KHz - 50 MHz) and high frequency (100 MHz 2 GHz) regions. Because the new material is in the form of a thin tape to properly characterize the tape it was necessary to separate the tape and substrate materials with a buried ground plane. Such separation was achieved by using a buried ground plane layer. A 1. 75 GHz microwave filter based on a dielectric tape fully integrated with the substrate was built using standard hybrid processes and thick film conductors. A good correlation was achieved between experimental results and computer modelling data.

Conductors for advanced packaging have thicknesses of the order of 6 microns and aspect ratios that are approaching 1: 1. These requirements are well within the capabilities of electrodeposition technology. The experience of the last decade in using electrodeposition to build thin-film recording heads which have similar and in some respects even more demanding specifications than packaging structures is directly applicable to the needs of packaging. This paper will show the application of resist-pattern plating to fabricating conductors for packaging will discuss the capabilities and limitations of resist-pattern plating plating and will indicate the parameters that need to be understood and controlled for the successful application of electrodeposition technology to microelectronic structures. A multi-level package structure can be considered as a repetition of several conductor and via levels. Each conductor/via level is made by first sputter depositing a seed layer of Cr/Cu in which the Cu is of the order of 2000 A thick. A layer of photoresist is then applied over the seed layer and openings are patterned in the resist to defme the conductor pattern. Electrical contact is now made to the seed layer and the part is immersed in an electroplating solution to deposit Cu in the openings defmed by the resist pattern. The thickness of the deposit is determined by the time and current density of plating the thickness of the photoresist must slightly exceed the desired

The accuracy of lumped element models for single RLC transmission lines is evaluated. To this end a new error criterion is proposed which permits to avaluate the accuracy of the models independent of driving and loading impedance levels. The results of the accuracy evaluation are represented in a concise way under form of a diagram and the use is illustrated by a typical example. In a second part of the paper examples of time domain simulations illustrate how the use of lumped element models can be extended to coupled lines with frequency dependent losses.

Analytical and numerical techniques formulated to model uniform and nonuniform lines are used to compute signal delays distortion and crosstalk in interconnects and packaging. The techniques presented include the use of CAD compatible circuit models and computational techniques based on time and frequency domain solution of multiconductor lossy interconnects. Typical numerical results for the pulse propagation characteristics of uniformly and nonuniformly coupled interconnects are presented.

The influence of conductor losses on the cross-talk between coupled microstrip lines is evaluated using an integral equation method. In this mathematical formulation the fields are computed inside the conductors and are utilized to define an equivalent impedance on the surface of the strips. This surface impedance is used as a boundary condition for the solution of the electromagnetic problem outside the conductors. Following this procedure the effect of losses on pulse dispersion in coupled microstrip lines is studied thoroughly for various geometries.

A weighted residual formulation for the transverse electric field is presented for the finite-element analysis of microstrip transmission lines on semiconductor substrates. The frequency dependence of the effective dielectric constant and the attenuation constant of the transmission lines are examined. The results from the full-wave analysis are used to determine when a quasi-TEM analysis is applicable.

Calculations of the electrical characteristics of the signal lines and other interconnects in computer modules have in the past often relied upon simplifying assumptions. For instance the quasi-TEM approximation or circuit models are often applied without proper consideration of the operating frequencies and coupling between package features. Though such approximations in most cases are probably valid it is difficult and time consuming to verify them. A better approach would be to employ a so!- ution technique that does not rely on such approximations in the the first place. This paper describes a rigorous approach to such modeling employing a full-wave Maxwell''s equation solution for determining the propagation characteristics of packages. Arbitrarily shaped 3-D signal lines and their discontinuities can be analyzed structures may include finite-size dielectric regions with material composition that may be anisotropic. The approach involves a method-of-moments solution technique with rooftop basis functions used to represent the surface current on the conductors and the polarization current in the dielectrics. To account for the dielectric regions the dielectric is first replaced by an array of interlocking thin-wall sections the electric field boundary conditions are later applied through the use of surface impedances. In the paper the signal propagation concerns in computer packages are first reviewed. Reflections off discontinuities proximity effects associated with nearby but nontouching other signal lines and vias (OLVs) and crosstalk and its sensitivity to various package parameters

When signals on a transmission line are divided two ways at a junction of three transmission lines multiple reflection waves will occur from impedance mismatching. This results in waveform distortions an increase in the effective risetime of input pulses and false triggering in high speed logical circuits. A transmission line network with a resistively matched 3port at a junction is discussed as a circuit which will furnish output waveforms similar within given tolerances to the waveform of the input. As transmission lines of unequal length are used here the network transfer functions include three different variables. However expansions of network transfer functions are presented with respect to the three variables. This enables us to calculate output responses. :i:

The skin effect of single and coupled conductor strips of finite thickness is analyzed using the dyadic Green''s function and integral equation formulation. Galerkin''s method is used to solve the integral equation for the dispersion characteristics. The effects of the geometrical and the electrical parameters on the conductor loss are investigated. Results are compared with literature and shown to be in good agreement. This approach is very useful for analyzing the electrical properties of interconnects in high performance computer circuitries.

High performance computers have been striving for higher speed better connectivity and higher throughput since their inception. Continuous advancement in the performance of active devices is placing an increasingly heavier demand on passive interconnects. This paper reviews optical interconnect technology in light of recent developments and suggests opportunities in datacom applications.

Analytical modeling and practical experience reveal that interconnection networks for large-scale parallel architectures are severely limited by the I/O bandwidth of electrical interconnects. Optical interconnects offer far greater potential in meeting these bandwidth demands. The development of an operational 1024x1024 polyimide waveguide perfect shuffle network and high-density modulator arrays demonstrate how optics can meet this challenge. Further optical switching networks would be possible with the development of single-mode 2x2 waveguide switches. We envisage as feasible the insertion of active optical interconnection networks in future large-scale parallel architectures using integrated arrays of waveguide modulators photodetectors switches and interconnects.

An investigation of potential physical design bottlenecks in future broadband telecommunication switches has led to the identification of several areas where optical interconnections may play a role in the practical realization of required system performance. In the model used the speed and interconnection densities as well as requirements for ease-of-access and efficient power utilization challenge conventional partitioning and packaging strategies. Potential areas where optical interconnections may relieve some of the physical design bottlenecks include fiber management at the customer interface to the switch routing and distribution of high-density interconnections within the fabric of the switch and backplane interconnections to increase system throughput.

Vertical-cavity surface-emitting lasers1 are generating much interest due to their geometric suitability for two-dimensional array fabrication and their potential for achieving ultra-low thresholds. Here we report on optically- and electrically-pumped microlaser devices. having transverse dimensions of a few microns and active material lengths of a few hundred A. The very small volumes are a key factor in achieving low thresholds. So far however surface recombination has prevented us from achieving thresholds much below 1 mA.

We have built and tested new multiple-layer silicon optical waveguide structures that have applications in wafer-scale optical interconnects. A repeated sequence of oxygen implantation annealing and Si epitaxy was used to make 5-layer or 6-layer structures containing a pair of 2- jim-thick Si waveguide cores separated by 1200A or 3700A of Si02. Coupled or uncoupled dual waveguiding at 1. 3 xm was observed. Inter-guide coupling for this stacked 3-D structure is analyzed here. Applications to all-silicon guided-wave optical interconnects are discussed.

The extremely compact PIN-amplifier module (6mm X 6mm X 8. 23mm) consisting of an InGaAs photodiode and a GaAs preamplifier IC has been developed. The ceramic sub-carrier having a GaAs IC on the top and a photodiode on the side was hermetically sealed into a kovar package which is provided a glass window. The characteristics of this module the combination of a transimpedance amplifier IC (1. Ok2 load) and a photodiode with lOOpm6 photosensitive area demonstrated the bandwidth of 770MHz and the sensitivity of - 29. 3dBm (at 622Mbps) and -27. 6dBm (at 1. 0625Gbps).

Optical micro-area networks (iANs) are proposed as a way of providing flexible communications among VLSI processors and eliminate electrical I/O bottlenecks. Sharedmedium multiple access protocols in jtANs can avoid the access delays associated with statistical multiple access protocols (which are unacceptable in multiprocessor applications) and increase the throughput at the expense of wasting optical bandwidth. Time-division multiple access (TDMA) may be more practical to implement in a pAN than other shared-medium multiple access protocols such as frequency-division or code-division. Since the total throughput of TDMA is given by the inverse of the optical pulsewidth the throughput can be increased by making the pulse width small. Accomplishing this goal requires avoiding the use of low-bandwidth electronics in the portion of the iAN that directly processes these short pulses. Instead optical processing can be used in those protions of the network. The architecture of a TDMA pAN which uses optical multiple access processing and is self-clocking is described in detail. Experimental demonstrations of key subsytems for optically generating modulating synchronizing delaying and correlating short optical pulses are presented. The feasibility of a variable-integer-delay line which provides rapid tuing wide tuning range and high precision is demonstrated. A transmitter consisting of a mode-locked laser with an external modulator is used in the TDMA iAN since arbitrarily short pulses can be controlled with a modulator that need only operate at the bit rate which translates

Two dimensional arrays of InGaAsIJnP based multiple quantum well surface modulators driven by standard high-speed CMOS have been demonstrated in experimental parallel optical interconnect and artificial neural processing systems. Transition times were fast enough for lOOMBit/s operation and the potential exists to increase array dimensions to include 100''s of devices and transmission rates to many GBit/s. Novel architectures employing computer generated holographic beam splitters and weight matrices outside the modulator and detector layers were employed.

Semiconductor quantum well devices are an important option for incorporating optics in digital systems. Some underlying reasons why optical devices can benefit digital systems are discussed. The potential for quantum well optical modulators and switches to help realize these benefits is summarized briefly. The importance of integration of optical and electronic components for any large scale use of optics in digital systems is emphasized.

Progress towards a free space interchip optical interconnect is described. We have fabricated an array of 36 differential optical receiver pairs in standard digital 0. 9 CMOS. The entire array occupies a square 2''lO on a side and each receiver channel can be operated up to 32OMbit/s. Link experiments are underway using these receivers in conjunction with transmitter arrays of GaAs SEEDs and microlasers. A compact opto-mechanical module for a simple system interconnect has also been designed constructed and tested.

In this presentation the requirements of a free-space optical bus for connecting electronic processors at the multichip module and board levels of interconnection are discussed. Experimental results for holographic elements suitable for beam division polarization switching and guided propagation are also described. The talk will conclude with an overview of CAD methods needed to incorporate these components into a bus system.

An approach is described to integrate optical systems on single substrates. It uses free-space optical propagation of the light signals inside the substrate and lithographically fabricated optical elements that can be aligned and mounted with submicron precision. Two-dimensional arrays of surface-emitting laser diodes and detector arrays can be used to implement integrated-optical backplanes in electronic multiprocessor systems or all-optical computers.

Computer generated holograms (CGH) and holographic optical elements (HOE) were fabricated onto thick photopolymer(Du Pont HRF films) to demonstrate interconnects architectures based on the hypercube and perfect shuffle designs. A 16element CGH Fresnel lens array was used to fabricate the multifacet holograms which are recorded as phase modulation because of the exposuredependent refractive index change of the photopolymer. The recording method can be applied to other holographic elements to be used for spacevariant optical interconnect configurations. I NTRODUCTI ON The need to overcome the interconnect bottleneck in massive parallel computing architectures has been the subject of much discussion. Free space optical interconnects based on CGH''s and HOE''s can potentially provide a practical solution to this problem[13]. They provide the possibility of implementing an arbitrary mapping using a single optical element. such a space variant interconnects topology can result in high degree of flexibility and interconnects density. One such an approach involves a 2D input array of processing elements(PE''s) each drives a semiconductor laser its beam is directed onto a HOE that images it into one or more photodetector located on an output array of PE''s. [4Similarly the system can be coherent[5] when the input array is spatial light modulator illuminated by a laser. This paper deals with the design and fabrication of transmission HOE''s for free space optical interconnects in two specific examples the hypercube and the perfect shuffle architectures.

A new design of GaAs/AlGaAs waveguide amplitude modulator intended for array applications at 830nm wavelength is reported. The device is based on polarization rotation and has bandwidths in excess of 1 GHz and an extinction ratio of 1 7dB. Mach-Zehnder modulators with 23dB have also been fabricated and arrays with 20 microns device separation fabricated. The arrays have crosstalk less than -20dB and feature electrical interconnection compatible with standard packaging techniques.

Electro-optic polymers exhibit many useful properties for distribution and routing of light on optical multilayer boards and modules. With the development of more robust materials it should soon be possible to use these materials to provide high-density interconnects at significant power savings and with reduced noise at frequencies above 100 MHz. We review the research toward creating new materials and devices for applications to packaging technology.

We have compared the optical loss characteristics of polyimide waveguides derived from three different polyimide samples. We observed significant differences in the waveguiding characteristics (at 0. 8 Rm) of these samples. The photosensitive preimidized samples exhibited the best waveguiding characteristics with losses below the detection limit (0. 5 dB/cm) in some instances. Various processing conditions such as the curing affected all three samples but to a different extent. The photosensitive polyamic acid ester based samples exhibited the maximum sensitivity to the curing temperature and the heating rate. Optical losses in the preimidized photosensitive polyimide films remained low (less than 1. 0 dB/cm) even after a 350 C baking step.

Optical packages with multiple optical I/Os and without optical pigtails or conventional connectors are proposed. These conceptual packages are of a hybrid PGA style with LSI chips and arrays of optical sources and detectors. A central theme is the use of only moderate extensions of current single chip and PWB packaging technologies. The light coupling between devices and waveguides is to be achieved using an array of lenses and/or microprisms. The feasibility of such a package is discussed from engineering manufacturing and repairability viewpoints.

Optical and 3D electronic implementations of a rearrangeably non-blocking permutation network are compared using complexity models. The electronic complexity model is based on the Thompson model for VLSI while the optical complexity model is new and based on the characteristics of optoelectronic devices and holographic optical elements. The analysis holds the manufacturing cost size and BER of the two implementations equal while comparing their latency. Whether optics is better than electronics depends on the message length.

Single chip microprocessor performance is projected to rise from around 32 bit 100 MIVs in 1990/1 towards 64 bit 1000 MIP''s by the end of the decade. New approaches to high speed parallel interconnections could clearly impact the exploitation of such massive computing power. In this paper we describe feasibility studies on optical interconnects. We explore the potential of optics to meet the speed power and crosstalk requirements for future VLSI IC interconnection. Indium Phosphide based quantum well modulators and photodetectors have been studied for coupling data to and from the I. C. Multimode waveguides are promising for the optical pathway.

Technological limitations appear in usual electrical interconnects (connector and electrical backplane) in new systems at the rack level. Optical solutions based on Holographic Optical Elements (HOE) on glass mastercard taking into account frequency and connectivity density limitations will be explained hereby. Also described is the realization solving both the tolerance problems (by an appropriate architecture) and the reliability of HOE (digital holograms). Original applications will be developed for reconfigurable interconnects between subassemblies of processors.

It is well known that dichromated gelatin (DCG) is one of the best recording media for the fabrication of holographic optical elements (HOEs). It has been used to make holographic interconnections position-tunable holographic filters and real-time multichannel multiplexed pattern recognition systems. After a short review on holographic interconnections and optical elements made in DCG we will show that methylene blue sensitized gelatin (MBG) with its enhanced red light sensitivity seems to be a more appropriate recording medium for the fabrication of HOEs to be used in the near-infrared.

A computer code has been developed for simulating light propagation in rectangular multimode waveguides of the type proposed for optical interconnections. Wave solutions are found by combining analytic slab waveguide modes and the Propagating Beam Method. Simulations will be demonstrated of a wide variety of passive optical circuit board devices such as 1-N splitters s-bends cross-throughs tapers and bends. The development of speckle from a coherent source the effect of source linewidth crosstalk and scattering will also be discussed.

Good alignment of the light beams and devices is necessary for maximum efficiency and reliability of an optical interconnection system. An optical interconnect which is difficult to align will be costly to manufacture and deploy. A measure of the ease with which a single beam of light and a device a basic optical interconnect can be aligned has been developed. This measure the alignability is a function of the beam size the spot size and the overall cost measure associated with the alignment. Practical optical interconnects consisting of several optical beams and devices such as optical crossbar switches can be modeled as series and parallel combinations of basic optical interconnects. The overall alignability can be obtained from the alignabilities of the component interconnects. A set of formulas for calculating component interconnects involving Gaussian and/or uniform beams and devices are derived. Using these formutas the alignability of several optical interconnection schemes and design and packaging guidelines can be developed.

The future aircraft generation will have thousand smart electromagnetic sensors distributed allover. Each sensor is connected with fibers links to the main-frame computer in charge of the real time signal''s correlation. Such a computer must be compactly built and massively parallel: it needs the use of 3 D optical free-space interconnect between neighbouring boards and reconfigurable interconnects via holographic backplane. The optical interconnect facilities will be also used to build fault-tolerant computer through large redundancy.

An optical receiver array containing 8 channels for optical interconnections is implemented in a silicon 1tm bipolar technology. It operates up to lGbit/s with an overall delay of 1. 4ns between optical signal input and full ECL level output. The fully DC-coupled channels need a photocurrent of 7tA to switch the logical level. Chip area and power consumption per channel correspond to 4 regular ECL gates.

Optical clock distribution is an attractive technique to avoid clock skew in highspeed digital systems. For short lengths free space distribution by holographic optical elements (HOE) has specific advantages. We will report on the requirements of the optical system in respect of necessary light power and its equipartition to the photoreceivers. We give an estimation for the maximum number for optical fanout con sidering especially ECL circuits. Specific system constraints lead to a certain layout for the whole arrangement. The realization of a distinct HOE type is carried out in form of a binary phase reflection HOE which is produced by dry etching of silicon. The measured diffraction efficiency is close to the theoretical limit.