Interconnection problems in VLSI random access memory chip

Venkatapathi Naidu Rayapati; Dinkar Mukhedkar

doi:10.1117/12.25513

1 April 1991 Interconnection problems in VLSI random access memory chip

Venkatapathi Naidu Rayapati, Dinkar Mukhedkar

Proceedings Volume 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies; (1991) https://doi.org/10.1117/12.25513
Event: Advances in Intelligent Robotics Systems, 1990, Boston, MA, United States

Abstract

This paper presents interconnection problems in VLSI Random Access Memory (RAM) chip. Interconnection effect on propagation delay speed power consumption and noise parameters are analyzed. Interconnect capacitance model is developed for VLSI RAM chip. A case study is presented for 1MB RAM chip interconnection problems. A multilevel interconnect approach is proposed to overcome onchip interconnect problems. The analysis results are found to be very useful for future mega bit RAMs. 98 / SPIE Vol. 1389 International Conference on Advances in Interconnection and Packaging (1990)

Citation Download Citation

Venkatapathi Naidu Rayapati and Dinkar Mukhedkar "Interconnection problems in VLSI random access memory chip", Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); https://doi.org/10.1117/12.25513

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