1 April 1991 Interconnection problems in VLSI random access memory chip
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Abstract
This paper presents interconnection problems in VLSI Random Access Memory (RAM) chip. Interconnection effect on propagation delay speed power consumption and noise parameters are analyzed. Interconnect capacitance model is developed for VLSI RAM chip. A case study is presented for 1MB RAM chip interconnection problems. A multilevel interconnect approach is proposed to overcome onchip interconnect problems. The analysis results are found to be very useful for future mega bit RAMs. 98 / SPIE Vol. 1389 International Conference on Advances in Interconnection and Packaging (1990)
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Venkatapathi Naidu Rayapati, Venkatapathi Naidu Rayapati, Dinkar Mukhedkar, Dinkar Mukhedkar, } "Interconnection problems in VLSI random access memory chip", Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25513; https://doi.org/10.1117/12.25513
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