1 April 1991 Interconnection problems in VLSI random access memory chip
Author Affiliations +
This paper presents interconnection problems in VLSI Random Access Memory (RAM) chip. Interconnection effect on propagation delay speed power consumption and noise parameters are analyzed. Interconnect capacitance model is developed for VLSI RAM chip. A case study is presented for 1MB RAM chip interconnection problems. A multilevel interconnect approach is proposed to overcome onchip interconnect problems. The analysis results are found to be very useful for future mega bit RAMs. 98 / SPIE Vol. 1389 International Conference on Advances in Interconnection and Packaging (1990)
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Venkatapathi Naidu Rayapati, Venkatapathi Naidu Rayapati, Dinkar Mukhedkar, Dinkar Mukhedkar, } "Interconnection problems in VLSI random access memory chip", Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25513; https://doi.org/10.1117/12.25513


Some fundamental issues on metallization in VLSI
Proceedings of SPIE (November 30 1991)
Mesoscopic noise in VLSI devices
Proceedings of SPIE (May 07 2003)
Reduced wire-length and routing complexity for LDPC decoders
Proceedings of SPIE (January 05 2006)
Optical receivers in ECL for 1GHz parallel links
Proceedings of SPIE (March 31 1991)

Back to Top