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1 March 1991 Spin-on-glass/phosphosilicate glass etchback planarization process for 1.0 um CMOS technology
Elizabeth Bogle-Rohwer; James E. Nulty; Wileen Chu; Andrew Cohen
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Proceedings Volume 1392, Advanced Techniques for Integrated Circuit Processing; (1991) https://doi.org/10.1117/12.48923
Event: Processing Integration, 1990, Santa Clara, CA, United States
Abstract
Studies of SOG/oxide planarization etch back processes have shown that micro loading effects play a major role in shifting selectivity of the etch at the SOG/oxide interface thereby causing the wafer to lose its asspun level of pianarization. This paper describes recent work performed to improve an SOG/PSG etchback planarizatiori process used in production on 1. O/m geome tries. The etchback planarization process is run in a Drytek Model 616 etch system using a triode chamber. In the study the effect of CHF3 C2F6 SF6 and CF4 gas chemistries on etch planarization are examined. Results of these experiments and how they compare to the original production etchback planarization process are discussed.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Elizabeth Bogle-Rohwer, James E. Nulty, Wileen Chu, and Andrew Cohen "Spin-on-glass/phosphosilicate glass etchback planarization process for 1.0 um CMOS technology", Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); https://doi.org/10.1117/12.48923
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