1 November 1990 Two case studies for Level Sensitive Scan Design methodology
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Proceedings Volume 1405, 5th Congress of the Brazilian Society of Microelectronics; (1990) https://doi.org/10.1117/12.26309
Event: 5th Congress of the Brazilian Society of Microelectronics, 1990, Sao Paulo, Brazil
Abstract
This work intend to provide an overview of some implementation aspects of Design of Testability through Level Sensitive Scan Design (LSSD) Techniques in two different IC designs developed by the IC Design Group at IBM Brasil Hardware Technology Center. Aspects include LSSD Design Methodology, test pin overhead, logic overhead, fault coverage, and test generation effort.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Celso F. V. Brites, Augusto C. F. Morais, "Two case studies for Level Sensitive Scan Design methodology", Proc. SPIE 1405, 5th Congress of the Brazilian Society of Microelectronics, (1 November 1990); doi: 10.1117/12.26309; https://doi.org/10.1117/12.26309
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