1 July 1991 Update on focal-plane image processing research
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An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2 of the total chip area and is performed using three parallel-serial-parallel (SP3) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP3 architecture, at an output rate of 83 X 103 pixels/sec. (0.9996 at 2 X 106 pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sabrina E. Kemeny, Sabrina E. Kemeny, Sayed I. Eid, Sayed I. Eid, Sunetra K. Mendis, Sunetra K. Mendis, Eric R. Fossum, Eric R. Fossum, } "Update on focal-plane image processing research", Proc. SPIE 1447, Charge-Coupled Devices and Solid State Optical Sensors II, (1 July 1991); doi: 10.1117/12.45329; https://doi.org/10.1117/12.45329

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