Investigation of interlevel proximity effects case of the gate level over LOCOS

Gilles Festes; Jean-Paul E. Chollet

doi:10.1117/12.44785

1 July 1991 Investigation of interlevel proximity effects case of the gate level over LOCOS

Gilles Festes, Jean-Paul E. Chollet

Proceedings Volume 1463, Optical/Laser Microlithography IV; (1991) https://doi.org/10.1117/12.44785
Event: Microlithography, 1991, San Jose, CA, United States

Abstract

Reflected light from steps causes defects in photolithography: extra exposure from a reflective nonplanar substrate induces resist profile damage and CD variations. This phenomenon, called the interlevel proximity effect, is studied for the standard case of polysilicon gate level over LOCOS level (local oxidation on silicon). The problem is extended to a parametric study. For each parameter, we have obtained an interval of critical gate-LOCOS distances in which the patterns are seriously affected. To explain the evaluated results, a simple and appropriate theoretical model is proposed, based on the oblique propagation of light rays. Finally, from the experimental conclusions, solutions to reduce notching are presented.

Citation Download Citation

Gilles Festes and Jean-Paul E. Chollet "Investigation of interlevel proximity effects case of the gate level over LOCOS", Proc. SPIE 1463, Optical/Laser Microlithography IV, (1 July 1991); https://doi.org/10.1117/12.44785

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