The aggressive drive to reduce device geometries to submicron levels while utilizing ULSI design rules has posed many challenges to traditional semiconductor process technologies. For example, as photolithographic hardware manufacturers, and engineers, begin to define and develop the next generation systems, it has become apparent that process margins are severely minimized with respect to the capability of existing hardware. As a result, all aspects of the process, especially the chemistry of the resist and develop modules, must be optimized and thoroughly understood to provide maximum process latitude. The work described in this publication details a process optimization effort that led to a manufacturable, single layer, G- line lithographic system capable of achieving and maintaining the necessary process control designated by aggressive design specifications. The photolithographic process was characterized using Advanced Engineering Techniques, as defined by Genichi Taguchi, in conjunction with Response Surface Methodology (RSM) multilevel statistical experimental designs. Optimized conditions resulted in a process capability of greater than 1.5 Cpk control when measured in reference to critical dimension performance. As a result, the newly defined system is capable of operating far beyond the scope of the more traditional systems, and has allowed for the manufacture of products necessary to compete in the advanced IC marketplace.