An experimental assessment of wafer flatness for 150 mm P/P+ epitaxial silicon wafers is presented to illustrate the use of graphical and analytical statistical techniques to both characterize and determine methods to reduce the variation in wafer flatness. This approach is applied to the chucked Local Total Indicator Reading (LTIR) site least squares front-reference plane for 354 P/P+ wafers and 144 P-type wafers from three suppliers measured over a range of site sizes (15 mm X 15 mm, 20 mm X 20 mm, 25 mm X 25 mm, and 20 mm X 30 mm). The objective is to ascertain the extent to which the lens total indicator range budget (taken as 1.1 micrometers as a figure of merit), is utilized by the silicon material. After taking into account estimates of the circuit topography and the lithographic machine detractors, an upper bound of 0.52 micrometers for the silicon LTIR was determined by an RMS analysis and a lower bound of 0.30 micrometers was taken as an approximation to a linear analysis. Histogram, cumulative frequency plots, and boxplot analysis for the sites on the wafers are presented. The importance of correcting for 'abnormal' site locations on the gauge chuck is noted. The percent variance components of flatness within a wafer, wafer to wafer in an epi run, epi run to epi run, polish lot to polish lot, and shipment to shipment is also presented. The source of the epi wafer percent variability appears to reside in the polished wafer substrate rather than be intrinsic to the epi process per se by comparing 'before' and 'after' epi wafer LTIR data.