Hierarchical proximity effect correction for e-beam direct writing of 64-Mbit DRAM

Akio Misaka; Kazuhiko Hashimoto; M. Kawamoto; H. Yamashita; Takahiro Matsuo; Toshihiko Sakashita; Kenji Harafuji; Noboru Nomura

doi:10.1117/12.47354

1 August 1991 Hierarchical proximity effect correction for e-beam direct writing of 64-Mbit DRAM

Akio Misaka, Kazuhiko Hashimoto, M. Kawamoto, H. Yamashita, Takahiro Matsuo, Toshihiko Sakashita, Kenji Harafuji, Noboru Nomura

Author Affiliations +

Proceedings Volume 1465, Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing; (1991) https://doi.org/10.1117/12.47354
Event: Microlithography, 1991, San Jose, CA, United States

Abstract

A high-speed proximity effect correction system with two-level cell hierarchy processing has been developed to realize an accuracy-assuring electron beam (EB) direct-writing for high density VLSI. The system has two distinct advantages. First, a new hierarchial zoning algorithm is introduced to realize a data compaction for the total pattern transactions. Zone data or assemblies or patterns to be proximity-corrected are created by the zoning procedure. Frame region is associated with each zone in order to incorporate the effect of back-scattered electrons into the zone data. Second, a fast iterative technique is introduced for the proximity effect correction calculation based on a dos modulation method. A double Gaussian proximity function is used for describing the electron scattering. The present correction system was applied to 64 Mbit DRAM pattern with a 0.4 micrometers design rule. The total correction processing for the layer with maximum data volume was completed within four hours in CPU time. The patterns after delineation and development were successfully obtained by combining the present proximity effect correction with tri-layer resist process.

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Akio Misaka, Kazuhiko Hashimoto, M. Kawamoto, H. Yamashita, Takahiro Matsuo, Toshihiko Sakashita, Kenji Harafuji, and Noboru Nomura "Hierarchical proximity effect correction for e-beam direct writing of 64-Mbit DRAM", Proc. SPIE 1465, Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing, (1 August 1991); https://doi.org/10.1117/12.47354

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