Multilevel qualitative reasoning in CMOS circuit analysis

Neeraj Kaul; Gautam Biswas

doi:10.1117/12.45466

1 March 1991 Multilevel qualitative reasoning in CMOS circuit analysis

Neeraj Kaul, Gautam Biswas

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Proceedings Volume 1468, Applications of Artificial Intelligence IX; (1991) https://doi.org/10.1117/12.45466
Event: Orlando '91, 1991, Orlando, FL, United States

Abstract

This paper develops a qualitative reasoning methodology for problem solving at multiple levels of abstraction. The goal is to address two important control issues in the behavior generation process: (i) the selection problem, which deals with the right level of detail to solve a problem, and (ii) the efficiency problem, which deals with information transfer from higher levels of abstraction to focus problem solving at more detailed levels. The CMOS digital circuit domain is used as a test bed to illustrate the methodologies developed.

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Neeraj Kaul, Neeraj Kaul, Gautam Biswas, Gautam Biswas, "Multilevel qualitative reasoning in CMOS circuit analysis", Proc. SPIE 1468, Applications of Artificial Intelligence IX, (1 March 1991); doi: 10.1117/12.45466; https://doi.org/10.1117/12.45466

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