A custom integrated circuit that performs imaging and feature extraction is under development as a component of an automatic object recognition system. Images are focussed directly onto the custom chip, which contains a photosensor array. On the same chip are structures to scan images out of the array, multiple lines at a time, in such a way as to present the image values of a small window of the array to a set of analog neural computational elements which are also on the chip. Each neuron sees the same image window as the others, but is controlled by an individual set of synaptic weights. Overlapping windows are sequentially scanned into the neurons, which develop a corresponding sequential set of outputs. These outputs represent a set of scanned feature maps, where the set of features is defined by the set of neural weights. Possible extracted features include oriented edges, lines, and points. The feature extraction computation is only the first step of a multi-level object recognition system, but the first stage requires large computational bandwidth. A 512 X 512 pixel imager with 16 neurons, each of which simultaneously looks at a 5 X 5 pixel window, is planned. The resulting data rate for 60 frames/sec is 6 billion multiplies and additions per second. This computation, and the imaging, will all be performed by a single chip. The authors have designed a simplified proof-of-concept chip that contains a 3 X 3 pixel imager hard-wired to a single neuron. The chip, in a simple imaging test fixture, demonstrates clearly the detection of simple features and illustrates the feasibility of combining neural processing circuitry on-chip with an imaging array.